]> git.zerfleddert.de Git - raggedstone/blame - dhwk/source/pci/verg_8.vhd
perl -p -i -e "s/PCI_CLOCK'event and PCI_CLOCK = '1'/rising_edge(PCI_CLOCK)/" *.vhd
[raggedstone] / dhwk / source / pci / verg_8.vhd
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11b038c2 1-- J.STELZNER
2-- INFORMATIK-3 LABOR
3-- 23.08.2006
4-- File: VERG_8.VHD
5
6library ieee;
7use ieee.std_logic_1164.all;
8
9entity VERG_8 is
10 port
11 (
12 GLEICH :in std_logic_vector(7 downto 0);
13 GLEICH_OUT :out std_logic
14 );
15
16end entity VERG_8;
17
18architecture VERG_8_DESIGN of VERG_8 is
19
20begin
21
22 -- GLEICH(0) nicht noetig. Addr-Bereich = 16 Byte
23
24 -- GLEICH_OUT <= '1' when GLEICH(7 downto 0) = "11111111" else '0';
25 GLEICH_OUT <= '1' when GLEICH(7 downto 1) = "1111111" else '0';
26
27end architecture VERG_8_DESIGN;
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