[raggedstone] / dhwk / source / fifo_control.vhd

-- VHDL model created from schematic fifo_control.sch -- Jan 09 09:34:17 2007\r
\r
\r
\r
LIBRARY ieee;\r
\r
USE ieee.std_logic_1164.ALL;\r
USE ieee.numeric_std.ALL;\r
\r
\r
entity FIFO_CONTROL is\r
      Port ( FIFO_RDn : In    std_logic;\r
             FLAG_IN_0 : In    std_logic;\r
             FLAG_IN_4 : In    std_logic;\r
                HOLD : In    std_logic;\r
             KONST_1 : In    std_logic;\r
             PCI_CLOCK : In    std_logic;\r
             PSC_ENABLE : In    std_logic;\r
               R_EFn : In    std_logic;\r
               R_FFn : In    std_logic;\r
               R_HFn : In    std_logic;\r
               RESET : In    std_logic;\r
               S_EFn : In    std_logic;\r
               S_FFn : In    std_logic;\r
             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
               S_HFn : In    std_logic;\r
             SERIAL_IN : In    std_logic;\r
             SPC_ENABLE : In    std_logic;\r
             SPC_RDY_IN : In    std_logic;\r
             WRITE_XX1_0 : In    std_logic;\r
             R_ERROR : Out   std_logic;\r
             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
             R_FIFO_READn : Out   std_logic;\r
             R_FIFO_RESETn : Out   std_logic;\r
             R_FIFO_RETRANSMITn : Out   std_logic;\r
             R_FIFO_WRITEn : Out   std_logic;\r
             RESERVE : Out   std_logic;\r
             S_ERROR : Out   std_logic;\r
             S_FIFO_READn : Out   std_logic;\r
             S_FIFO_RESETn : Out   std_logic;\r
             S_FIFO_RETRANSMITn : Out   std_logic;\r
             S_FIFO_WRITEn : Out   std_logic;\r
             SERIAL_OUT : Out   std_logic;\r
             SPC_RDY_OUT : Out   std_logic;\r
             SR_ERROR : Out   std_logic;\r
             SYNC_FLAG : Out   std_logic_vector (7 downto 0);\r
	     PAR_SER_IN : Out std_logic_vector (7 downto 0);\r
	     SER_PAR_OUT : Out std_logic_vector (7 downto 0));\r
end FIFO_CONTROL;\r
\r
architecture SCHEMATIC of FIFO_CONTROL is\r
\r
   SIGNAL gnd : std_logic := '0';\r
   SIGNAL vcc : std_logic := '1';\r
\r
   signal XXXR_FIFO_WRITEn : std_logic;\r
   signal XXXS_FIFO_READn : std_logic;\r
   signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);\r
   signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);\r
   signal watcher : std_logic_vector (7 downto 0);\r
\r
   component SER_PAR_CON\r
      Port ( PCI_CLOCK : In    std_logic;\r
               RESET : In    std_logic;\r
             SERIAL_IN : In    std_logic;\r
             SPC_ENABLE : In    std_logic;\r
             SYNC_R_FIFO_FFn : In    std_logic;\r
             PAR_OUT : Out   std_logic_vector (7 downto 0);\r
             R_FIFO_WRITEn : Out   std_logic;\r
             SPC_RDY_OUT : Out   std_logic );\r
   end component;\r
\r
   component PAR_SER_CON\r
      Port (  PAR_IN : In    std_logic_vector (7 downto 0);\r
             PCI_CLOCK : In    std_logic;\r
             PSC_ENABLE : In    std_logic;\r
               RESET : In    std_logic;\r
             SPC_RDY_IN : In    std_logic;\r
             SYNC_S_FIFO_EFn : In    std_logic;\r
             S_FIFO_READn : Out   std_logic;\r
             SER_OUT : Out   std_logic );\r
   end component;\r
\r
   component FIFO_IO_CONTROL\r
      Port ( FIFO_RDn : In    std_logic;\r
             PCI_CLOCK : In    std_logic;\r
               RESET : In    std_logic;\r
             SYNC_FLAG_1 : In    std_logic;\r
             SYNC_FLAG_7 : In    std_logic;\r
             WRITE_XX1_0 : In    std_logic;\r
             R_ERROR : Out   std_logic;\r
             R_FIFO_READn : Out   std_logic;\r
             R_FIFO_RESETn : Out   std_logic;\r
             R_FIFO_RETRANSMITn : Out   std_logic;\r
             S_ERROR : Out   std_logic;\r
             S_FIFO_RESETn : Out   std_logic;\r
             S_FIFO_RETRANSMITn : Out   std_logic;\r
             S_FIFO_WRITEn : Out   std_logic;\r
             SR_ERROR : Out   std_logic );\r
   end component;\r
\r
   component CONNECTING_FSM\r
      Port ( PCI_CLOCK : In    std_logic;\r
             PSC_ENABLE : In    std_logic;\r
               RESET : In    std_logic;\r
             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
             SPC_ENABLE : In    std_logic;\r
             SYNC_R_FIFO_FFn : In    std_logic;\r
             SYNC_S_FIFO_EFn : In    std_logic;\r
             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
             R_FIFO_WRITEn : Out   std_logic;\r
             S_FIFO_READn : Out   std_logic );\r
   end component;\r
\r
   component FLAG_BUS\r
      Port ( FLAG_IN_0 : In    std_logic;\r
             FLAG_IN_4 : In    std_logic;\r
                HOLD : In    std_logic;\r
              KONS_1 : In    std_logic;\r
             PCI_CLOCK : In    std_logic;\r
               R_EFn : In    std_logic;\r
               R_FFn : In    std_logic;\r
               R_HFn : In    std_logic;\r
               S_EFn : In    std_logic;\r
               S_FFn : In    std_logic;\r
               S_HFn : In    std_logic;\r
             SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
   end component;\r
\r
begin\r
\r
   SYNC_FLAG <= SYNC_FLAG_DUMMY;\r
   PAR_SER_IN <= S_FIFO_Q_OUT;\r
   SER_PAR_OUT <= watcher;\r
   R_FIFO_D_IN(7 downto 0) <= watcher;\r
\r
   RESERVE <= gnd;\r
   I23 : SER_PAR_CON\r
      Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
                 SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,\r
                 SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
                 PAR_OUT(7 downto 0)=>watcher,\r
                 R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );\r
   I22 : PAR_SER_CON\r
      Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
                 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,\r
                 RESET=>RESET, SPC_RDY_IN=>SPC_RDY_IN,\r
                 SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),\r
                 S_FIFO_READn=>S_FIFO_READn, SER_OUT=>SERIAL_OUT );\r
   I21 : FIFO_IO_CONTROL\r
      Port Map ( FIFO_RDn=>FIFO_RDn, PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
                 SYNC_FLAG_1=>SYNC_FLAG_DUMMY(1),\r
                 SYNC_FLAG_7=>SYNC_FLAG_DUMMY(7),\r
                 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
                 R_FIFO_READn=>R_FIFO_READn,\r
                 R_FIFO_RESETn=>R_FIFO_RESETn,\r
                 R_FIFO_RETRANSMITn=>R_FIFO_RETRANSMITn,\r
                 S_ERROR=>S_ERROR, S_FIFO_RESETn=>S_FIFO_RESETn,\r
                 S_FIFO_RETRANSMITn=>S_FIFO_RETRANSMITn,\r
                 S_FIFO_WRITEn=>S_FIFO_WRITEn, SR_ERROR=>SR_ERROR );\r
   I20 : CONNECTING_FSM\r
      Port Map ( PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,\r
                 RESET=>RESET,\r
                 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
                 SPC_ENABLE=>SPC_ENABLE,\r
                 SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
                 SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),\r
                 R_FIFO_D_IN(7 downto 0)=>XXXR_FIFO_D_IN(7 downto 0),\r
                 R_FIFO_WRITEn=>XXXR_FIFO_WRITEn,\r
                 S_FIFO_READn=>XXXS_FIFO_READn );\r
   I19 : FLAG_BUS\r
      Port Map ( FLAG_IN_0=>FLAG_IN_0, FLAG_IN_4=>FLAG_IN_4, HOLD=>HOLD,\r
                 KONS_1=>KONST_1, PCI_CLOCK=>PCI_CLOCK, R_EFn=>R_EFn,\r
                 R_FFn=>R_FFn, R_HFn=>R_HFn, S_EFn=>S_EFn, S_FFn=>S_FFn,\r
                 S_HFn=>S_HFn,\r
                 SYNC_FLAG(7 downto 0)=>SYNC_FLAG_DUMMY(7 downto 0) );\r
\r
end SCHEMATIC;\r
Commit	Line	Data
377c0242	1	-- VHDL model created from schematic fifo_control.sch -- Jan 09 09:34:17 2007\r
	2	\r
	3	\r
	4	\r
	5	LIBRARY ieee;\r
	6	\r
	7	USE ieee.std_logic_1164.ALL;\r
	8	USE ieee.numeric_std.ALL;\r
	9	\r
	10	\r
	11	entity FIFO_CONTROL is\r
	12	Port ( FIFO_RDn : In std_logic;\r
	13	FLAG_IN_0 : In std_logic;\r
	14	FLAG_IN_4 : In std_logic;\r
	15	HOLD : In std_logic;\r
	16	KONST_1 : In std_logic;\r
	17	PCI_CLOCK : In std_logic;\r
	18	PSC_ENABLE : In std_logic;\r
	19	R_EFn : In std_logic;\r
	20	R_FFn : In std_logic;\r
	21	R_HFn : In std_logic;\r
	22	RESET : In std_logic;\r
	23	S_EFn : In std_logic;\r
	24	S_FFn : In std_logic;\r
	25	S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
	26	S_HFn : In std_logic;\r
	27	SERIAL_IN : In std_logic;\r
	28	SPC_ENABLE : In std_logic;\r
	29	SPC_RDY_IN : In std_logic;\r
	30	WRITE_XX1_0 : In std_logic;\r
	31	R_ERROR : Out std_logic;\r
	32	R_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
	33	R_FIFO_READn : Out std_logic;\r
	34	R_FIFO_RESETn : Out std_logic;\r
	35	R_FIFO_RETRANSMITn : Out std_logic;\r
	36	R_FIFO_WRITEn : Out std_logic;\r
	37	RESERVE : Out std_logic;\r
	38	S_ERROR : Out std_logic;\r
	39	S_FIFO_READn : Out std_logic;\r
	40	S_FIFO_RESETn : Out std_logic;\r
	41	S_FIFO_RETRANSMITn : Out std_logic;\r
	42	S_FIFO_WRITEn : Out std_logic;\r
	43	SERIAL_OUT : Out std_logic;\r
	44	SPC_RDY_OUT : Out std_logic;\r
	45	SR_ERROR : Out std_logic;\r
a76e12bd	46	SYNC_FLAG : Out std_logic_vector (7 downto 0);\r
f822aceb	47	PAR_SER_IN : Out std_logic_vector (7 downto 0);\r
f822aceb	48	SER_PAR_OUT : Out std_logic_vector (7 downto 0));\r
377c0242	49	end FIFO_CONTROL;\r
	50	\r
	51	architecture SCHEMATIC of FIFO_CONTROL is\r
	52	\r
	53	SIGNAL gnd : std_logic := '0';\r
	54	SIGNAL vcc : std_logic := '1';\r
	55	\r
	56	signal XXXR_FIFO_WRITEn : std_logic;\r
	57	signal XXXS_FIFO_READn : std_logic;\r
	58	signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);\r
	59	signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);\r
f822aceb	60	signal watcher : std_logic_vector (7 downto 0);\r
377c0242	61	\r
	62	component SER_PAR_CON\r
	63	Port ( PCI_CLOCK : In std_logic;\r
	64	RESET : In std_logic;\r
	65	SERIAL_IN : In std_logic;\r
	66	SPC_ENABLE : In std_logic;\r
	67	SYNC_R_FIFO_FFn : In std_logic;\r
	68	PAR_OUT : Out std_logic_vector (7 downto 0);\r
	69	R_FIFO_WRITEn : Out std_logic;\r
	70	SPC_RDY_OUT : Out std_logic );\r
	71	end component;\r
	72	\r
	73	component PAR_SER_CON\r
	74	Port ( PAR_IN : In std_logic_vector (7 downto 0);\r
	75	PCI_CLOCK : In std_logic;\r
	76	PSC_ENABLE : In std_logic;\r
	77	RESET : In std_logic;\r
	78	SPC_RDY_IN : In std_logic;\r
	79	SYNC_S_FIFO_EFn : In std_logic;\r
	80	S_FIFO_READn : Out std_logic;\r
	81	SER_OUT : Out std_logic );\r
	82	end component;\r
	83	\r
	84	component FIFO_IO_CONTROL\r
	85	Port ( FIFO_RDn : In std_logic;\r
	86	PCI_CLOCK : In std_logic;\r
	87	RESET : In std_logic;\r
	88	SYNC_FLAG_1 : In std_logic;\r
	89	SYNC_FLAG_7 : In std_logic;\r
	90	WRITE_XX1_0 : In std_logic;\r
	91	R_ERROR : Out std_logic;\r
	92	R_FIFO_READn : Out std_logic;\r
	93	R_FIFO_RESETn : Out std_logic;\r
	94	R_FIFO_RETRANSMITn : Out std_logic;\r
	95	S_ERROR : Out std_logic;\r
	96	S_FIFO_RESETn : Out std_logic;\r
	97	S_FIFO_RETRANSMITn : Out std_logic;\r
	98	S_FIFO_WRITEn : Out std_logic;\r
	99	SR_ERROR : Out std_logic );\r
	100	end component;\r
	101	\r
	102	component CONNECTING_FSM\r
	103	Port ( PCI_CLOCK : In std_logic;\r
	104	PSC_ENABLE : In std_logic;\r
	105	RESET : In std_logic;\r
	106	S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
	107	SPC_ENABLE : In std_logic;\r
	108	SYNC_R_FIFO_FFn : In std_logic;\r
	109	SYNC_S_FIFO_EFn : In std_logic;\r
	110	R_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
	111	R_FIFO_WRITEn : Out std_logic;\r
	112	S_FIFO_READn : Out std_logic );\r
	113	end component;\r
	114	\r
	115	component FLAG_BUS\r
	116	Port ( FLAG_IN_0 : In std_logic;\r
	117	FLAG_IN_4 : In std_logic;\r
	118	HOLD : In std_logic;\r
	119	KONS_1 : In std_logic;\r
	120	PCI_CLOCK : In std_logic;\r
	121	R_EFn : In std_logic;\r
	122	R_FFn : In std_logic;\r
	123	R_HFn : In std_logic;\r
	124	S_EFn : In std_logic;\r
125	S_FFn : In std_logic;\r
126	S_HFn : In std_logic;\r
127	SYNC_FLAG : Out std_logic_vector (7 downto 0) );\r
128	end component;\r
129	\r
130	begin\r
131	\r
132	SYNC_FLAG <= SYNC_FLAG_DUMMY;\r
a76e12bd	133	PAR_SER_IN <= S_FIFO_Q_OUT;\r
f822aceb	134	SER_PAR_OUT <= watcher;\r
f822aceb	135	R_FIFO_D_IN(7 downto 0) <= watcher;\r
377c0242	136	\r
	137	RESERVE <= gnd;\r
	138	I23 : SER_PAR_CON\r
	139	Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
	140	SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,\r
	141	SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
f822aceb	142	PAR_OUT(7 downto 0)=>watcher,\r
377c0242	143	R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );\r
	144	I22 : PAR_SER_CON\r
	145	Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
	146	PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,\r
	147	RESET=>RESET, SPC_RDY_IN=>SPC_RDY_IN,\r
	148	SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),\r
	149	S_FIFO_READn=>S_FIFO_READn, SER_OUT=>SERIAL_OUT );\r
	150	I21 : FIFO_IO_CONTROL\r
	151	Port Map ( FIFO_RDn=>FIFO_RDn, PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
	152	SYNC_FLAG_1=>SYNC_FLAG_DUMMY(1),\r
	153	SYNC_FLAG_7=>SYNC_FLAG_DUMMY(7),\r
	154	WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
	155	R_FIFO_READn=>R_FIFO_READn,\r
	156	R_FIFO_RESETn=>R_FIFO_RESETn,\r
	157	R_FIFO_RETRANSMITn=>R_FIFO_RETRANSMITn,\r
	158	S_ERROR=>S_ERROR, S_FIFO_RESETn=>S_FIFO_RESETn,\r
	159	S_FIFO_RETRANSMITn=>S_FIFO_RETRANSMITn,\r
	160	S_FIFO_WRITEn=>S_FIFO_WRITEn, SR_ERROR=>SR_ERROR );\r
	161	I20 : CONNECTING_FSM\r
	162	Port Map ( PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,\r
	163	RESET=>RESET,\r
	164	S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
	165	SPC_ENABLE=>SPC_ENABLE,\r
	166	SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
	167	SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),\r
	168	R_FIFO_D_IN(7 downto 0)=>XXXR_FIFO_D_IN(7 downto 0),\r
	169	R_FIFO_WRITEn=>XXXR_FIFO_WRITEn,\r
	170	S_FIFO_READn=>XXXS_FIFO_READn );\r
	171	I19 : FLAG_BUS\r
	172	Port Map ( FLAG_IN_0=>FLAG_IN_0, FLAG_IN_4=>FLAG_IN_4, HOLD=>HOLD,\r
	173	KONS_1=>KONST_1, PCI_CLOCK=>PCI_CLOCK, R_EFn=>R_EFn,\r
	174	R_FFn=>R_FFn, R_HFn=>R_HFn, S_EFn=>S_EFn, S_FFn=>S_FFn,\r
	175	S_HFn=>S_HFn,\r
	176	SYNC_FLAG(7 downto 0)=>SYNC_FLAG_DUMMY(7 downto 0) );\r
	177	\r
	178	end SCHEMATIC;\r