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[raggedstone] / dhwk / source / fifo_control.vhd
1 -- VHDL model created from schematic fifo_control.sch -- Jan 09 09:34:17 2007
2
3
4
5 LIBRARY ieee;
6
7 USE ieee.std_logic_1164.ALL;
8 USE ieee.numeric_std.ALL;
9
10
11 entity FIFO_CONTROL is
12 Port ( FIFO_RDn : In std_logic;
13 FLAG_IN_0 : In std_logic;
14 FLAG_IN_4 : In std_logic;
15 HOLD : In std_logic;
16 KONST_1 : In std_logic;
17 PCI_CLOCK : In std_logic;
18 PSC_ENABLE : In std_logic;
19 R_EFn : In std_logic;
20 R_FFn : In std_logic;
21 R_HFn : In std_logic;
22 RESET : In std_logic;
23 S_EFn : In std_logic;
24 S_FFn : In std_logic;
25 S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
26 S_HFn : In std_logic;
27 SERIAL_IN : In std_logic;
28 SPC_ENABLE : In std_logic;
29 SPC_RDY_IN : In std_logic;
30 WRITE_XX1_0 : In std_logic;
31 R_ERROR : Out std_logic;
32 R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
33 R_FIFO_READn : Out std_logic;
34 R_FIFO_RESETn : Out std_logic;
35 R_FIFO_RETRANSMITn : Out std_logic;
36 R_FIFO_WRITEn : Out std_logic;
37 RESERVE : Out std_logic;
38 S_ERROR : Out std_logic;
39 S_FIFO_READn : Out std_logic;
40 S_FIFO_RESETn : Out std_logic;
41 S_FIFO_RETRANSMITn : Out std_logic;
42 S_FIFO_WRITEn : Out std_logic;
43 SERIAL_OUT : Out std_logic;
44 SPC_RDY_OUT : Out std_logic;
45 SR_ERROR : Out std_logic;
46 SYNC_FLAG : Out std_logic_vector (7 downto 0);
47 PAR_SER_IN : Out std_logic_vector (7 downto 0);
48 SER_PAR_OUT : Out std_logic_vector (7 downto 0));
49 end FIFO_CONTROL;
50
51 architecture SCHEMATIC of FIFO_CONTROL is
52
53 SIGNAL gnd : std_logic := '0';
54 SIGNAL vcc : std_logic := '1';
55
56 signal XXXR_FIFO_WRITEn : std_logic;
57 signal XXXS_FIFO_READn : std_logic;
58 signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);
59 signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);
60 signal watcher : std_logic_vector (7 downto 0);
61
62 component SER_PAR_CON
63 Port ( PCI_CLOCK : In std_logic;
64 RESET : In std_logic;
65 SERIAL_IN : In std_logic;
66 SPC_ENABLE : In std_logic;
67 SYNC_R_FIFO_FFn : In std_logic;
68 PAR_OUT : Out std_logic_vector (7 downto 0);
69 R_FIFO_WRITEn : Out std_logic;
70 SPC_RDY_OUT : Out std_logic );
71 end component;
72
73 component PAR_SER_CON
74 Port ( PAR_IN : In std_logic_vector (7 downto 0);
75 PCI_CLOCK : In std_logic;
76 PSC_ENABLE : In std_logic;
77 RESET : In std_logic;
78 SPC_RDY_IN : In std_logic;
79 SYNC_S_FIFO_EFn : In std_logic;
80 S_FIFO_READn : Out std_logic;
81 SER_OUT : Out std_logic );
82 end component;
83
84 component FIFO_IO_CONTROL
85 Port ( FIFO_RDn : In std_logic;
86 PCI_CLOCK : In std_logic;
87 RESET : In std_logic;
88 SYNC_FLAG_1 : In std_logic;
89 SYNC_FLAG_7 : In std_logic;
90 WRITE_XX1_0 : In std_logic;
91 R_ERROR : Out std_logic;
92 R_FIFO_READn : Out std_logic;
93 R_FIFO_RESETn : Out std_logic;
94 R_FIFO_RETRANSMITn : Out std_logic;
95 S_ERROR : Out std_logic;
96 S_FIFO_RESETn : Out std_logic;
97 S_FIFO_RETRANSMITn : Out std_logic;
98 S_FIFO_WRITEn : Out std_logic;
99 SR_ERROR : Out std_logic );
100 end component;
101
102 component CONNECTING_FSM
103 Port ( PCI_CLOCK : In std_logic;
104 PSC_ENABLE : In std_logic;
105 RESET : In std_logic;
106 S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
107 SPC_ENABLE : In std_logic;
108 SYNC_R_FIFO_FFn : In std_logic;
109 SYNC_S_FIFO_EFn : In std_logic;
110 R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
111 R_FIFO_WRITEn : Out std_logic;
112 S_FIFO_READn : Out std_logic );
113 end component;
114
115 component FLAG_BUS
116 Port ( FLAG_IN_0 : In std_logic;
117 FLAG_IN_4 : In std_logic;
118 HOLD : In std_logic;
119 KONS_1 : In std_logic;
120 PCI_CLOCK : In std_logic;
121 R_EFn : In std_logic;
122 R_FFn : In std_logic;
123 R_HFn : In std_logic;
124 S_EFn : In std_logic;
125 S_FFn : In std_logic;
126 S_HFn : In std_logic;
127 SYNC_FLAG : Out std_logic_vector (7 downto 0) );
128 end component;
129
130 begin
131
132 SYNC_FLAG <= SYNC_FLAG_DUMMY;
133 PAR_SER_IN <= S_FIFO_Q_OUT;
134 SER_PAR_OUT <= watcher;
135 R_FIFO_D_IN(7 downto 0) <= watcher;
136
137 RESERVE <= gnd;
138 I23 : SER_PAR_CON
139 Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,
140 SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,
141 SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),
142 PAR_OUT(7 downto 0)=>watcher,
143 R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );
144 I22 : PAR_SER_CON
145 Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
146 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,
147 RESET=>RESET, SPC_RDY_IN=>SPC_RDY_IN,
148 SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),
149 S_FIFO_READn=>S_FIFO_READn, SER_OUT=>SERIAL_OUT );
150 I21 : FIFO_IO_CONTROL
151 Port Map ( FIFO_RDn=>FIFO_RDn, PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,
152 SYNC_FLAG_1=>SYNC_FLAG_DUMMY(1),
153 SYNC_FLAG_7=>SYNC_FLAG_DUMMY(7),
154 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
155 R_FIFO_READn=>R_FIFO_READn,
156 R_FIFO_RESETn=>R_FIFO_RESETn,
157 R_FIFO_RETRANSMITn=>R_FIFO_RETRANSMITn,
158 S_ERROR=>S_ERROR, S_FIFO_RESETn=>S_FIFO_RESETn,
159 S_FIFO_RETRANSMITn=>S_FIFO_RETRANSMITn,
160 S_FIFO_WRITEn=>S_FIFO_WRITEn, SR_ERROR=>SR_ERROR );
161 I20 : CONNECTING_FSM
162 Port Map ( PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,
163 RESET=>RESET,
164 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
165 SPC_ENABLE=>SPC_ENABLE,
166 SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),
167 SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),
168 R_FIFO_D_IN(7 downto 0)=>XXXR_FIFO_D_IN(7 downto 0),
169 R_FIFO_WRITEn=>XXXR_FIFO_WRITEn,
170 S_FIFO_READn=>XXXS_FIFO_READn );
171 I19 : FLAG_BUS
172 Port Map ( FLAG_IN_0=>FLAG_IN_0, FLAG_IN_4=>FLAG_IN_4, HOLD=>HOLD,
173 KONS_1=>KONST_1, PCI_CLOCK=>PCI_CLOCK, R_EFn=>R_EFn,
174 R_FFn=>R_FFn, R_HFn=>R_HFn, S_EFn=>S_EFn, S_FFn=>S_FFn,
175 S_HFn=>S_HFn,
176 SYNC_FLAG(7 downto 0)=>SYNC_FLAG_DUMMY(7 downto 0) );
177
178 end SCHEMATIC;
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