[raggedstone] / dhwk_old / source / sync.v

module sync2 (clk, d, q);
	input clk;
	input d;
	output q;
	reg	q;

	always @(posedge clk)
	begin
		q <= d;
	end
endmodule
Commit	Line	Data
ebba63a9	1	module sync2 (clk, d, q);
	2	input clk;
	3	input d;
	4	output q;
	5	reg q;
	6
	7	always @(posedge clk)
	8	begin
	9	q <= d;
	10	end
	11	endmodule