first import of dhwk.
[raggedstone] / dhwk / source / REG.vhd
... / ...
CommitLineData
1-- J.STELZNER\r
2-- INFORMATIK-3 LABOR\r
3-- 23.08.2006\r
4-- File: REG.VHD\r
5\r
6library ieee ;\r
7use ieee.std_logic_1164.all ;\r
8\r
9entity REG is\r
10 port\r
11 (\r
12 CLOCK :in std_logic; \r
13 RESET :in std_logic; \r
14 WRITE :in std_logic; \r
15 REG_IN :in std_logic_vector(7 downto 0);\r
16 REG_OUT :out std_logic_vector(7 downto 0) \r
17 );\r
18end entity REG ;\r
19\r
20architecture REG_DESIGN of REG is\r
21\r
22 signal SIG_REG :std_logic_vector (7 downto 0);\r
23\r
24begin\r
25\r
26 process (CLOCK) \r
27 begin\r
28 if (CLOCK'event and CLOCK = '1') then\r
29 if RESET = '1' then SIG_REG <= X"00";\r
30 elsif WRITE = '1' then SIG_REG <= REG_IN;\r
31 else SIG_REG <= SIG_REG;\r
32 end if;\r
33 end if;\r
34 end process;\r
35\r
36 REG_OUT <= SIG_REG;\r
37\r
38end architecture REG_DESIGN;\r
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