first import of dhwk.
authorsithglan <sithglan>
Sat, 10 Mar 2007 11:24:03 +0000 (11:24 +0000)
committersithglan <sithglan>
Sat, 10 Mar 2007 11:24:03 +0000 (11:24 +0000)
46 files changed:
dhwk/Makefile [new file with mode: 0644]
dhwk/dhwk.prj [new file with mode: 0644]
dhwk/dhwk.ucf [new file with mode: 0644]
dhwk/dhwk.ut [new file with mode: 0644]
dhwk/dhwk.xst [new file with mode: 0644]
dhwk/source/Addr_regi.vhd [new file with mode: 0644]
dhwk/source/COMM_DEC.vhd [new file with mode: 0644]
dhwk/source/COMM_FSM.vhd [new file with mode: 0644]
dhwk/source/CONT_FSM.vhd [new file with mode: 0644]
dhwk/source/DATA_MUX.vhd [new file with mode: 0644]
dhwk/source/FLAG_BUS.vhd [new file with mode: 0644]
dhwk/source/INTERRUPT.vhd [new file with mode: 0644]
dhwk/source/IO_RW_SEL.vhd [new file with mode: 0644]
dhwk/source/Io_mux.vhd [new file with mode: 0644]
dhwk/source/Io_reg.vhd [new file with mode: 0644]
dhwk/source/MESS_1_TB.vhd [new file with mode: 0644]
dhwk/source/PAR_SER_CON.vhd [new file with mode: 0644]
dhwk/source/Parity_4.vhd [new file with mode: 0644]
dhwk/source/REG.vhd [new file with mode: 0644]
dhwk/source/SER_PAR_CON.vhd [new file with mode: 0644]
dhwk/source/Verg_2.vhd [new file with mode: 0644]
dhwk/source/Verg_4.vhd [new file with mode: 0644]
dhwk/source/config_00h.vhd [new file with mode: 0644]
dhwk/source/config_04h.vhd [new file with mode: 0644]
dhwk/source/config_08h.vhd [new file with mode: 0644]
dhwk/source/config_10h.vhd [new file with mode: 0644]
dhwk/source/config_3Ch.vhd [new file with mode: 0644]
dhwk/source/config_mux_0.vhd [new file with mode: 0644]
dhwk/source/config_rd_0.vhd [new file with mode: 0644]
dhwk/source/config_space_header.vhd [new file with mode: 0644]
dhwk/source/config_wr_0.vhd [new file with mode: 0644]
dhwk/source/connecting_fsm.vhd [new file with mode: 0644]
dhwk/source/fifo_control.vhd [new file with mode: 0644]
dhwk/source/fifo_io_control.vhd [new file with mode: 0644]
dhwk/source/io_mux_reg.vhd [new file with mode: 0644]
dhwk/source/parity.vhd [new file with mode: 0644]
dhwk/source/parity_out.vhd [new file with mode: 0644]
dhwk/source/pci_interface.vhd [new file with mode: 0644]
dhwk/source/pci_top.vhd [new file with mode: 0644]
dhwk/source/reg_io.vhd [new file with mode: 0644]
dhwk/source/steuerung.vhd [new file with mode: 0644]
dhwk/source/synplify.vhd [new file with mode: 0644]
dhwk/source/top.vhd [new file with mode: 0644]
dhwk/source/user_io.vhd [new file with mode: 0644]
dhwk/source/verg_8.vhd [new file with mode: 0644]
dhwk/source/vergleich.vhd [new file with mode: 0644]

diff --git a/dhwk/Makefile b/dhwk/Makefile
new file mode 100644 (file)
index 0000000..0bf5c98
--- /dev/null
@@ -0,0 +1,3 @@
+PROJECT := raggedstone
+
+include ../common/Makefile.common
diff --git a/dhwk/dhwk.prj b/dhwk/dhwk.prj
new file mode 100644 (file)
index 0000000..9e1460e
--- /dev/null
@@ -0,0 +1,41 @@
+vhdl work "source/verg_8.vhd"
+vhdl work "source/synplify.vhd"
+vhdl work "source/parity_out.vhd"
+vhdl work "source/config_wr_0.vhd"
+vhdl work "source/config_rd_0.vhd"
+vhdl work "source/config_mux_0.vhd"
+vhdl work "source/config_3Ch.vhd"
+vhdl work "source/config_10h.vhd"
+vhdl work "source/config_08h.vhd"
+vhdl work "source/config_04h.vhd"
+vhdl work "source/config_00h.vhd"
+vhdl work "source/Verg_4.vhd"
+vhdl work "source/Verg_2.vhd"
+vhdl work "source/REG.vhd"
+vhdl work "source/Parity_4.vhd"
+vhdl work "source/Io_reg.vhd"
+vhdl work "source/Io_mux.vhd"
+vhdl work "source/CONT_FSM.vhd"
+vhdl work "source/COMM_FSM.vhd"
+vhdl work "source/COMM_DEC.vhd"
+vhdl work "source/Addr_regi.vhd"
+vhdl work "source/vergleich.vhd"
+vhdl work "source/steuerung.vhd"
+vhdl work "source/reg_io.vhd"
+vhdl work "source/parity.vhd"
+vhdl work "source/io_mux_reg.vhd"
+vhdl work "source/config_space_header.vhd"
+vhdl work "source/IO_RW_SEL.vhd"
+vhdl work "source/DATA_MUX.vhd"
+vhdl work "source/user_io.vhd"
+vhdl work "source/pci_interface.vhd"
+vhdl work "source/fifo_io_control.vhd"
+vhdl work "source/connecting_fsm.vhd"
+vhdl work "source/SER_PAR_CON.vhd"
+vhdl work "source/PAR_SER_CON.vhd"
+vhdl work "source/FLAG_BUS.vhd"
+vhdl work "source/pci_top.vhd"
+vhdl work "source/fifo_control.vhd"
+vhdl work "source/MESS_1_TB.vhd"
+vhdl work "source/INTERRUPT.vhd"
+vhdl work "source/top.vhd"
diff --git a/dhwk/dhwk.ucf b/dhwk/dhwk.ucf
new file mode 100644 (file)
index 0000000..9f9ac54
--- /dev/null
@@ -0,0 +1,52 @@
+NET "LED2"  LOC = "AB5" | IOSTANDARD = LVCMOS33 ;
+NET "LED3"  LOC = "AA5" | IOSTANDARD = LVCMOS33 ;
+NET "PCI_AD<0>"  LOC = "A5" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<10>"  LOC = "E9" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<11>"  LOC = "F11" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<12>"  LOC = "E10" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<13>"  LOC = "A8" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<14>"  LOC = "B9" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<15>"  LOC = "B10" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<16>"  LOC = "F17" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<17>"  LOC = "F16" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<18>"  LOC = "A14" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<19>"  LOC = "B14" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<1>"  LOC = "B5" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<20>"  LOC = "B15" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<21>"  LOC = "A15" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<22>"  LOC = "F12" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<23>"  LOC = "F13" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<24>"  LOC = "D15" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<25>"  LOC = "E15" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<26>"  LOC = "D17" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<27>"  LOC = "C17" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<28>"  LOC = "B17" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<29>"  LOC = "E17" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<2>"  LOC = "E6" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<30>"  LOC = "A18" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<31>"  LOC = "B18" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<3>"  LOC = "D6" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<4>"  LOC = "C6" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<5>"  LOC = "B6" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<6>"  LOC = "D7" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<7>"  LOC = "E7" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<8>"  LOC = "B8" | IOSTANDARD = PCI33_3 ;
+NET "PCI_AD<9>"  LOC = "F10" | IOSTANDARD = PCI33_3 ;
+NET "PCI_CBE<0>"  LOC = "F9" | IOSTANDARD = PCI33_3 ;
+NET "PCI_CBE<1>"  LOC = "C10" | IOSTANDARD = PCI33_3 ;
+NET "PCI_CBE<2>"  LOC = "D13" | IOSTANDARD = PCI33_3 ;
+NET "PCI_CBE<3>"  LOC = "E13" | IOSTANDARD = PCI33_3 ;
+NET "PCI_CLK"  LOC = "A11" | IOSTANDARD = PCI33_3 ;
+NET "PCI_IDSEL"  LOC = "D14" | IOSTANDARD = PCI33_3 ;
+NET "PCI_nDEVSEL"  LOC = "E12" | IOSTANDARD = PCI33_3 ;
+NET "PCI_nFRAME"  LOC = "C13" | IOSTANDARD = PCI33_3 ;
+NET "PCI_nINT"  LOC = "B19" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
+NET "PCI_nIRDY"  LOC = "A13" | IOSTANDARD = PCI33_3 ;
+NET "PCI_nPERR"  LOC = "D12" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
+NET "PCI_nRES"  LOC = "A19" | IOSTANDARD = PCI33_3 ;
+NET "PCI_nSERR"  LOC = "B12" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
+NET "PCI_nSTOP"  LOC = "A12" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
+NET "PCI_nTRDY"  LOC = "B13" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
+NET "PCI_PAR"  LOC = "A9" | IOSTANDARD = PCI33_3  | SLEW = FAST ;
+NET "LED5"  LOC = "AB4" | IOSTANDARD = LVCMOS33 ;
+NET "LED4"  LOC = "AA4" | IOSTANDARD = LVCMOS33 ;
diff --git a/dhwk/dhwk.ut b/dhwk/dhwk.ut
new file mode 100644 (file)
index 0000000..1a6b102
--- /dev/null
@@ -0,0 +1,27 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:6
+-g CclkPin:PullUp
+-g M0Pin:PullUp
+-g M1Pin:PullUp
+-g M2Pin:PullUp
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullUp
+-g UserID:0xFFFFFFFF
+-g DCIUpdateMode:AsRequired
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
diff --git a/dhwk/dhwk.xst b/dhwk/dhwk.xst
new file mode 100644 (file)
index 0000000..9a47866
--- /dev/null
@@ -0,0 +1,51 @@
+set -xsthdpdir ./xst
+run
+-ifn dhwk.prj
+-ifmt mixed
+-ofn dhwk
+-ofmt NGC
+-p xc3s1500-fg456-4
+-top dhwk
+-opt_mode Speed
+-opt_level 1
+-iuc NO
+-lso dhwk.lso
+-keep_hierarchy NO
+-glob_opt AllClockNets
+-rtlview Yes
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case maintain
+-slice_utilization_ratio 100
+-verilog2001 YES
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style lut
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-rom_style Auto
+-mux_extract YES
+-decoder_extract YES
+-priority_extract YES
+-shreg_extract YES
+-shift_extract YES
+-xor_collapse YES
+-resource_sharing YES
+-mult_style auto
+-iobuf YES
+-max_fanout 500
+-bufg 8
+-register_duplication YES
+-equivalent_register_removal YES
+-register_balancing No
+-slice_packing YES
+-optimize_primitives NO
+-use_clock_enable Yes
+-use_sync_set Yes
+-use_sync_reset Yes
+-iob auto
+-slice_utilization_ratio_maxmargin 5
diff --git a/dhwk/source/Addr_regi.vhd b/dhwk/source/Addr_regi.vhd
new file mode 100644 (file)
index 0000000..143c7b5
--- /dev/null
@@ -0,0 +1,43 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: ADDR_REG.VHD\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity ADDR_REGI is\r
+       port\r
+       (\r
+       PCI_CLOCK                       :in             std_logic;\r
+       PCI_RSTn                        :in             std_logic;\r
+       LOAD_ADDR_REG   :in             std_logic;\r
+       AD_REG                          :in             std_logic_vector (31 downto 0);\r
+       ADDR_REG                        :out    std_logic_vector (31 downto 0)\r
+  );\r
+end entity ADDR_REGI;\r
+\r
+architecture ADDR_REGI_DESIGN of ADDR_REGI is\r
+\r
+       signal  REG_ADDR        :std_logic_vector (31 downto 0); \r
+\r
+begin \r
+\r
+       process (PCI_CLOCK, PCI_RSTn) \r
+       begin\r
+               if      PCI_RSTn = '0'  then    REG_ADDR        <= X"00000000";\r
+\r
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
+\r
+                       if LOAD_ADDR_REG = '1' then\r
+                                               REG_ADDR        <=      AD_REG;\r
+\r
+                       else    REG_ADDR        <=      REG_ADDR;\r
+                       end if;\r
+\r
+               end if;\r
+       end process;\r
+\r
+       ADDR_REG        <=      REG_ADDR;\r
+\r
+end architecture ADDR_REGI_DESIGN;\r
diff --git a/dhwk/source/COMM_DEC.vhd b/dhwk/source/COMM_DEC.vhd
new file mode 100644 (file)
index 0000000..d2f423a
--- /dev/null
@@ -0,0 +1,141 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: COMM_DEC.VHD\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all ;\r
+\r
+entity COMM_DEC is\r
+       port\r
+       (\r
+       PCI_CLOCK               :in             std_logic; \r
+       PCI_RSTn                :in             std_logic; \r
+       MY_ADDR                 :in             std_logic;\r
+       IDSEL_REG               :in             std_logic;\r
+       FRAME_REGn      :in             std_logic;\r
+       IO_SPACE                :in             std_logic;\r
+       AD_REG                  :in             std_logic_vector(31 downto 0);\r
+       CBE_REGn                :in             std_logic_vector( 3 downto 0);\r
+       LAR                                     :out    std_logic;--LOAD_ADDR_REG\r
+       IO_READ                 :out    std_logic;\r
+       IO_WRITE                :out    std_logic;\r
+       CONF_READ               :out    std_logic;\r
+       CONF_WRITE      :out    std_logic;\r
+       SERR_CHECK      :out    std_logic\r
+       );\r
+end entity COMM_DEC ;\r
+\r
+architecture COMM_DEC_DESIGN of COMM_DEC is\r
+\r
+\r
+--PCI Bus Commands \r
+--C/BE[3..0] Command Type\r
+--------------------------------------\r
+--     0000            Interrupt Acknowledge\r
+--     0001            Special Cycle\r
+--     0010            I/O Read\r
+--     0011            I/O Write\r
+--     0100            Reserved\r
+--     0101            Reserved\r
+--     0110            Memory Read\r
+--     0111            Memory Write\r
+--\r
+--     1000            Reserved\r
+--     1001            Reserved\r
+--     1010            Configuration Read\r
+--     1011            Configuration Write\r
+--     1100            Memory Read Multiple \r
+--     1101            Dual Address Cycle\r
+--     1110            Memory Read Line\r
+--     1111            Memory Write and Invalidate\r
+\r
+\r
+--PCI Byte Enable \r
+--C/BE[3..0] gueltige Datenbits \r
+-------------------------------\r
+--     0000            AD 31..0\r
+--     1000            AD 23..0\r
+--     1100            AD 15..0\r
+--     1110            AD  7..0\r
+\r
+       constant        cmd_int_ack                     :std_logic_vector(3 downto 0) := "0000";\r
+       constant        cmd_sp_cyc                      :std_logic_vector(3 downto 0) := "0001";\r
+       constant        cmd_io_read                     :std_logic_vector(3 downto 0) := "0010";\r
+       constant        cmd_io_write            :std_logic_vector(3 downto 0) := "0011";\r
+       constant        cmd_res_4                               :std_logic_vector(3 downto 0) := "0100";\r
+       constant        cmd_res_5                               :std_logic_vector(3 downto 0) := "0101";\r
+       constant        cmd_mem_read            :std_logic_vector(3 downto 0) := "0110";\r
+       constant        cmd_mem_write           :std_logic_vector(3 downto 0) := "0111";\r
+       constant        cmd_res_8                               :std_logic_vector(3 downto 0) := "1000";\r
+       constant        cmd_res_9                               :std_logic_vector(3 downto 0) := "1001";\r
+       constant        cmd_conf_read           :std_logic_vector(3 downto 0) := "1010";\r
+       constant        cmd_conf_write  :std_logic_vector(3 downto 0) := "1011";\r
+       constant        cmd_mem_read_m  :std_logic_vector(3 downto 0) := "1100";\r
+       constant        cmd_du_adr_cyc  :std_logic_vector(3 downto 0) := "1101";\r
+       constant        cmd_mem_read_l  :std_logic_vector(3 downto 0) := "1110";\r
+       constant        cmd_mem_write_i :std_logic_vector(3 downto 0) := "1111";\r
+\r
+       signal          START                                           :std_logic; \r
+       signal          FRAME_REG_REGn  :std_logic; \r
+\r
+       signal          SIG_IO_READ                     :std_logic; \r
+       signal          SIG_IO_WRITE            :std_logic; \r
+       signal          SIG_CONF_READ           :std_logic; \r
+       signal          SIG_CONF_WRITE  :std_logic; \r
+\r
+begin\r
+\r
+       process (PCI_CLOCK, PCI_RSTn) \r
+       begin\r
+               if      PCI_RSTn = '0'  then    FRAME_REG_REGn  <=      '1';    \r
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
+\r
+                       FRAME_REG_REGn  <=      FRAME_REGn; \r
+\r
+               end if;\r
+       end process;\r
+\r
+\r
+       START                   <= (not FRAME_REGn) and FRAME_REG_REGn; \r
+\r
+\r
+\r
+       SIG_IO_READ             <= '1'  when    START                   = '1'\r
+                                                                                               and             IO_SPACE        = '1'\r
+                                                                                               and             CBE_REGn        = cmd_io_read   \r
+                                                                                               and             MY_ADDR         = '1'\r
+                                                       else '0'; \r
+\r
+\r
+       SIG_IO_WRITE    <= '1'  when    START                   = '1'\r
+                                                                                               and             IO_SPACE        = '1'\r
+                                                                                               and             CBE_REGn        = cmd_io_write\r
+                                                                                               and             MY_ADDR         = '1'\r
+                                                       else '0'; \r
+\r
+\r
+       SIG_CONF_READ   <= '1'  when    START                                                           = '1'\r
+                                                                                               and             AD_REG(1 downto 0)      = "00"\r
+                                                                                               and             CBE_REGn                                                = cmd_conf_read\r
+                                                                                               and             IDSEL_REG                                               = '1'\r
+                                                                                               \r
+                                               else '0'; \r
+\r
+\r
+       SIG_CONF_WRITE  <= '1'  when    START                                                           = '1'\r
+                                                                                                       and             AD_REG(1 downto 0)      = "00"\r
+                                                                                                       and             CBE_REGn                                                = cmd_conf_write\r
+                                                                                                       and             IDSEL_REG                                               = '1'\r
+                                                               else '0'; \r
+\r
+       LAR                     <=      START;\r
+\r
+       SERR_CHECK      <= SIG_IO_READ or SIG_IO_WRITE or SIG_CONF_READ or SIG_CONF_WRITE;       \r
+\r
+       IO_READ         <=      SIG_IO_READ;\r
+       IO_WRITE        <=      SIG_IO_WRITE;    \r
+       CONF_READ         <=    SIG_CONF_READ;  \r
+       CONF_WRITE      <=      SIG_CONF_WRITE;\r
+\r
+end architecture COMM_DEC_DESIGN ;\r
diff --git a/dhwk/source/COMM_FSM.vhd b/dhwk/source/COMM_FSM.vhd
new file mode 100644 (file)
index 0000000..158426e
--- /dev/null
@@ -0,0 +1,98 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: COMM_FSM.VHD\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all ;\r
+\r
+entity COMM_FSM is\r
+       port\r
+       (\r
+       PCI_CLOCK               :in             std_logic; \r
+       PCI_RSTn                :in             std_logic; \r
+       IO_READ                 :in             std_logic;\r
+       IO_WRITE                :in             std_logic;\r
+       CONF_READ               :in             std_logic;\r
+       CONF_WRITE      :in             std_logic;\r
+       DEVSELn                 :in             std_logic;      \r
+\r
+       IO_RD_COM       :       out     std_logic;--> MUX_SEL(0)                                                      \r
+       CF_RD_COM       :out    std_logic; \r
+       IO_WR_COM               :out    std_logic;     \r
+       CF_WR_COM               :out    std_logic \r
+       );\r
+end entity COMM_FSM ;\r
+\r
+architecture COMM_FSM_DESIGN of COMM_FSM is\r
+\r
+\r
+--**********************************************************\r
+--***            COMMAND FSM CODIERUNG                   ***\r
+--**********************************************************\r
+--\r
+--\r
+--                                                                        |--------- IO_RD_COM                                                    \r
+--                                                                        ||-------- CF_RD_COM   \r
+--                                                                                    |||------- IO_WR_COM   \r
+--                                                                                ||||------ CF_WR_COM   \r
+--                                                                            ||||     \r
+       constant        ST_IDLE_COMM    :std_logic_vector (3 downto 0) := "0000" ;-- \r
+       constant        ST_CONF_WRITE   :std_logic_vector (3 downto 0) := "0001" ;-- \r
+       constant        ST_IO_WRITE             :std_logic_vector (3 downto 0) := "0010" ;-- \r
+       constant        ST_CONF_READ    :std_logic_vector (3 downto 0) := "0100" ;-- \r
+       constant        ST_IO_READ              :std_logic_vector (3 downto 0) := "1000" ;--\r
+\r
+       signal          COMM_STATE              :std_logic_vector (3 downto 0);\r
+\r
+--************************************************************\r
+--***             FSM SPEICHER-AUTOMAT                     ***\r
+--************************************************************\r
+\r
+       attribute syn_state_machine : boolean;\r
+       attribute syn_state_machine of COMM_STATE : signal is false;\r
+\r
+begin\r
+\r
+--**********************************************************\r
+--***                   COMMAND FSM                        ***\r
+--**********************************************************\r
+\r
+       process (PCI_CLOCK, PCI_RSTn) \r
+       begin\r
+               if      PCI_RSTn = '0'  then    COMM_STATE      <= "0000";\r
+\r
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
\r
+                       case COMM_STATE is\r
+       \r
+                               when ST_IDLE_COMM => \r
+                                       if              IO_READ                         = '1' then                                                      COMM_STATE <= ST_IO_READ;\r
+\r
+                               elsif   CONF_READ               = '1' then                                                      COMM_STATE <= ST_CONF_READ; \r
+\r
+                                               elsif   IO_WRITE                = '1' then                                                      COMM_STATE <= ST_IO_WRITE;   \r
+  \r
+                               elsif   CONF_WRITE      = '1' then                                                      COMM_STATE <= ST_CONF_WRITE;     \r
+\r
+                   else                                                                                                                                                COMM_STATE <= ST_IDLE_COMM;\r
+                                       end if;                                                 \r
+       \r
+                               when ST_IO_READ                 => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;             \r
+                               when ST_CONF_READ               => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;             \r
+                               when ST_IO_WRITE                => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;             \r
+                               when ST_CONF_WRITE      => if DEVSELn = '1' then        COMM_STATE <= ST_IDLE_COMM; end if;\r
+       \r
+                               when others =>                                                                                                                          COMM_STATE <= ST_IDLE_COMM; \r
+\r
+                       end case;               -- COMM_STATE    \r
+               end if;                         -- CLOCK   \r
+       end process;            -- PROCESS\r
+\r
+       IO_RD_COM       <=      COMM_STATE(3);                                                     \r
+       CF_RD_COM       <=      COMM_STATE(2);      \r
+       IO_WR_COM       <=      COMM_STATE(1);      \r
+       CF_WR_COM       <=      COMM_STATE(0);      \r
+       \r
+end architecture COMM_FSM_DESIGN ;\r
+\r
diff --git a/dhwk/source/CONT_FSM.vhd b/dhwk/source/CONT_FSM.vhd
new file mode 100644 (file)
index 0000000..67fc8a7
--- /dev/null
@@ -0,0 +1,156 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: CONT_FSM.VHD\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all ;\r
+\r
+entity CONT_FSM is\r
+       port\r
+       (\r
+       PCI_CLOCK               :in             std_logic; \r
+       PCI_RSTn                :in             std_logic; \r
+       IO_READ                 :in             std_logic;\r
+       IO_WRITE                :in             std_logic;\r
+       CONF_READ               :in             std_logic;\r
+       CONF_WRITE      :in             std_logic;\r
+       FIFO_READ               :in             std_logic;\r
+       READ                            :out    std_logic;--> MUX_SEL(1) , OE_PCI_AD \r
+       PERR_CHECK      :out    std_logic;              \r
+       DEVSELn                 :out    std_logic;\r
+       OE_PCI_PAR      :out    std_logic;\r
+       OE_PCI_PERR     :out    std_logic;\r
+       TRDYn                           :out    std_logic;\r
+       PCI_TRDYn               :out    std_logic;      --      s/t/s\r
+       PCI_STOPn               :out    std_logic;      --      s/t/s   \r
+       PCI_DEVSELn     :out    std_logic;      --      s/t/s   \r
+       FIFO_RDn                :out    std_logic\r
+       );\r
+end entity CONT_FSM ;\r
+\r
+architecture CONT_FSM_DESIGN of CONT_FSM is\r
+\r
+\r
+\r
+--**********************************************************\r
+--***              CONTROL FSM CODIERUNG                 ***\r
+--**********************************************************\r
+--\r
+--\r
+--\r
+--                                                           |----------- HELP\r
+--                                                           ||---------- FIFO_READn\r
+--                                                           |||--------- OE_PCI_PERR          \r
+--                                                                                                      ||||-------- PERR_CHECK  \r
+--                                                                                                              |||||------- TRDYn   \r
+--                                                                                                                ||||||------ STOPn                                                    \r
+--                                                                                                              |||||||----- DEVSELn   \r
+--                                                                                        ||||||||---- OE_PCI_PAR   \r
+--                                                                                                                                                                                                                              |||||||||--- OE_CONTROL   \r
+--                                                                                                                                                                                                                                ||||||||||-- READ / MUX_SEL(1) / OE_PCI_AD \r
+--                                                                                                                                                                                                                                      ||||||||||               \r
+       constant        ST_IDLE :std_logic_vector (9 downto 0) := "0100111000" ;-- 138\r
+\r
+       constant        ST_READ_1                       :std_logic_vector (9 downto 0) := "0100110011" ;-- 133\r
+       constant        ST_READ_2                       :std_logic_vector (9 downto 0) := "0100000111" ;-- 107\r
+       constant        ST_READ_3                       :std_logic_vector (9 downto 0) := "0100111111" ;-- 13F\r
+\r
+       constant        ST_RD_FIFO_1    :std_logic_vector (9 downto 0) := "0000110011" ;-- 033\r
+       constant        ST_RD_FIFO_2    :std_logic_vector (9 downto 0) := "1000110011" ;-- 233\r
+\r
+\r
+       constant        ST_WRITE_1              :std_logic_vector (9 downto 0) := "0111110010" ;-- 1F2\r
+       constant        ST_WRITE_2              :std_logic_vector (9 downto 0) := "0110000010" ;-- 182\r
+       constant        ST_WRITE_3              :std_logic_vector (9 downto 0) := "0110111010" ;-- 1BA\r
+\r
+       signal          CONTROL_STATE   :std_logic_vector (9 downto 0);\r
+\r
+\r
+--signal               DEVSELn                 :std_logic;\r
+       signal          STOPn                   :std_logic;\r
+--signal               TRDYn                   :std_logic;\r
+\r
+--************************************************************\r
+--***             FSM SPEICHER-AUTOMAT                     ***\r
+--************************************************************\r
+\r
+       attribute syn_state_machine : boolean;\r
+       attribute syn_state_machine of CONTROL_STATE : signal is false;\r
+\r
+begin\r
+\r
+--**********************************************************\r
+--***                  CONTROL FSM                       ***\r
+--**********************************************************\r
+\r
+       process (PCI_CLOCK, PCI_RSTn) \r
+       begin\r
+               if      PCI_RSTn = '0'  then    CONTROL_STATE   <= ST_IDLE;\r
+\r
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
\r
+                       case CONTROL_STATE is\r
+       \r
+                               when ST_IDLE => \r
+                                       if                      IO_READ         = '1' then\r
+                                                                                                                       CONTROL_STATE <= ST_READ_1;\r
+\r
+                               elsif   CONF_READ       = '1' then\r
+                                                                                                                       CONTROL_STATE <= ST_READ_1; \r
+\r
+                                               elsif   IO_WRITE        = '1' then\r
+                                                                                                                       CONTROL_STATE <= ST_WRITE_1;   \r
+  \r
+                               elsif   CONF_WRITE      = '1' then\r
+                                                                                                                       CONTROL_STATE <= ST_WRITE_1;\r
+     \r
+                       else                                            CONTROL_STATE <= ST_IDLE;\r
+                                       end if; \r
+\r
+--                     when    ST_READ_1               =>      CONTROL_STATE   <=      ST_READ_2;\r
+                               when    ST_READ_1               =>      \r
+                                       if                      FIFO_READ       = '1' then\r
+                                                                                                                       CONTROL_STATE <= ST_RD_FIFO_1;\r
+                                               else                                            CONTROL_STATE <= ST_READ_2;\r
+                                       end if; \r
+\r
+\r
+                               when    ST_READ_2               =>      CONTROL_STATE   <=      ST_READ_3;\r
+                               when    ST_READ_3               =>      CONTROL_STATE   <=      ST_IDLE;\r
+\r
+                               when    ST_RD_FIFO_1=>  CONTROL_STATE   <=      ST_RD_FIFO_2;\r
+                               when    ST_RD_FIFO_2=>  CONTROL_STATE   <=      ST_READ_2;\r
+\r
+\r
+        \r
+                               when    ST_WRITE_1      =>      CONTROL_STATE   <=      ST_WRITE_2;\r
+                               when    ST_WRITE_2      =>      CONTROL_STATE   <=      ST_WRITE_3;\r
+                               when    ST_WRITE_3      =>      CONTROL_STATE   <=      ST_IDLE;\r
+\r
+               \r
+                               when others                             =>      CONTROL_STATE   <=      ST_IDLE; \r
+\r
+                       end case;               -- COMM_STATE    \r
+               end if;                         -- CLOCK   \r
+       end process;                    -- PROCESS\r
+\r
+\r
+       READ                            <=      CONTROL_STATE(0);\r
+--OE_CONTROL   <=      CONTROL_STATE(1);\r
+       OE_PCI_PAR      <=      CONTROL_STATE(2);\r
+       DEVSELn                 <=      CONTROL_STATE(3);\r
+       STOPn                           <=      CONTROL_STATE(4);\r
+       TRDYn                           <=      CONTROL_STATE(5);\r
+       PERR_CHECK      <=      CONTROL_STATE(6);\r
+       OE_PCI_PERR     <=      CONTROL_STATE(7);\r
+\r
+       FIFO_RDn                <=      CONTROL_STATE(8);\r
+\r
+\r
+       PCI_DEVSELn     <=      CONTROL_STATE(3)        when    CONTROL_STATE(1) = '1' else 'Z';\r
+       PCI_STOPn       <=      STOPn                                   when    CONTROL_STATE(1) = '1' else 'Z';                                                                      \r
+       PCI_TRDYn         <=    CONTROL_STATE(5)        when    CONTROL_STATE(1) = '1' else 'Z';        \r
+\r
+end architecture CONT_FSM_DESIGN ;\r
+\r
diff --git a/dhwk/source/DATA_MUX.vhd b/dhwk/source/DATA_MUX.vhd
new file mode 100644 (file)
index 0000000..46632e2
--- /dev/null
@@ -0,0 +1,77 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: DATA_MUX.VHD\r
+\r
+library ieee ;\r
+use ieee.std_logic_1164.all ;\r
\r
+entity DATA_MUX is\r
+       port\r
+       (\r
+       READ_SEL                :in             std_logic_vector( 1 downto 0);\r
+       ADDR_REG                :in             std_logic_vector(31 downto 0);\r
+       CBE_REGn                :in             std_logic_vector( 3 downto 0);\r
+       MUX_IN_XX0      :in             std_logic_vector( 7 downto 0);\r
+       MUX_IN_XX1      :in             std_logic_vector( 7 downto 0);\r
+       MUX_IN_XX2      :in             std_logic_vector( 7 downto 0);\r
+       MUX_IN_XX3      :in             std_logic_vector( 7 downto 0);\r
+       MUX_IN_XX4      :in             std_logic_vector( 7 downto 0);\r
+       MUX_IN_XX5      :in             std_logic_vector( 7 downto 0);\r
+       MUX_IN_XX6      :in             std_logic_vector( 7 downto 0);\r
+       MUX_IN_XX7      :in             std_logic_vector( 7 downto 0);\r
+       MUX_OUT                 :out    std_logic_vector(31 downto 0);\r
+       READ_XX1_0      :out    std_logic;      \r
+       READ_XX3_2      :out    std_logic;\r
+       READ_XX5_4      :out    std_logic;\r
+       READ_XX7_6      :out    std_logic\r
+--READ_FIFO            :out    std_logic\r
+       );\r
+end entity DATA_MUX ;\r
+\r
+architecture DATA_MUX_DESIGN of DATA_MUX is\r
+\r
+       signal  MUX     :std_logic_vector(31 downto 0);\r
+       signal  SEL     :std_logic_vector( 7 downto 0);\r
+\r
+       signal  SIG_READ_XX1_0  :std_logic;\r
+       signal  SIG_READ_XX3_2  :std_logic;\r
+       signal  SIG_READ_XX5_4  :std_logic;\r
+       signal  SIG_READ_XX7_6  :std_logic;\r
+\r
+begin\r
+\r
+       SEL     <= ADDR_REG(3 downto 2) & CBE_REGn      &       READ_SEL ;      \r
+                                                                                                                                                                                                                                                                               \r
+       SIG_READ_XX1_0  <=      '1' when        SEL     =       "00110011"      else    '0';\r
+       SIG_READ_XX3_2  <=      '1' when        SEL     =       "00001111"      else    '0';\r
+       SIG_READ_XX5_4  <=      '1' when        SEL     =       "01110011"      else    '0';\r
+       SIG_READ_XX7_6  <=      '1' when        SEL     =       "01001111"      else    '0';\r
+\r
+\r
+                                                                       \r
+       MUX     <=      (X"00"                  & X"00"                         & MUX_IN_XX1    &       MUX_IN_XX0)     when    SIG_READ_XX1_0  =       '1' else \r
+                                       (MUX_IN_XX3     &       MUX_IN_XX2  &   X"00"                           & X"00"                 )       when    SIG_READ_XX3_2  =       '1' else                                \r
+                                       (X"00"                  & X"00"                         & MUX_IN_XX5    &       MUX_IN_XX4)     when    SIG_READ_XX5_4  =       '1' else \r
+                                       (MUX_IN_XX7     &       MUX_IN_XX6  &   X"00"                           & X"00"                 )       when    SIG_READ_XX7_6  =       '1' else        \r
+                                       (others => '0');                                                                                                                                                                                                                                                                                                \r
+\r
+\r
+--     MUX     <=      (X"01"                  & X"23"                         & MUX_IN_XX1    &       MUX_IN_XX0)     when    SIG_READ_XX1_0  =       '1' else \r
+--                                     (MUX_IN_XX3     &       MUX_IN_XX2  &   X"45"                           & X"67"                 )       when    SIG_READ_XX3_2  =       '1' else                                \r
+--                                     (X"89"                  & X"AB"                         & MUX_IN_XX5    &       MUX_IN_XX4)     when    SIG_READ_XX5_4  =       '1' else \r
+--                                     (MUX_IN_XX7     &       MUX_IN_XX6  &   X"CD"                           & X"EF"                 )       when    SIG_READ_XX7_6  =       '1' else        \r
+--                                     (others => '0');                                                                                                                                                                                                                                                                                                \r
+\r
+\r
+       MUX_OUT <= MUX ;\r
+\r
+\r
+       READ_XX1_0      <=      SIG_READ_XX1_0;                 \r
+       READ_XX3_2      <=      SIG_READ_XX3_2;\r
+       READ_XX5_4      <=      SIG_READ_XX5_4;\r
+       READ_XX7_6      <=      SIG_READ_XX7_6;\r
+\r
+--READ_FIFO            <=      SIG_READ_XX3_2 or SIG_READ_XX5_4;--SIG_READ_XX5_4 nur fuer test\r
+\r
+end architecture DATA_MUX_DESIGN ;\r
diff --git a/dhwk/source/FLAG_BUS.vhd b/dhwk/source/FLAG_BUS.vhd
new file mode 100644 (file)
index 0000000..c312be7
--- /dev/null
@@ -0,0 +1,98 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: FLAG_BUS.VHD\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity FLAG_BUS is\r
+       port\r
+       (\r
+       PCI_CLOCK       :in             std_logic;\r
+       KONS_1          :in             std_logic;\r
+       FLAG_IN_0       :in             std_logic;\r
+       R_EFn                   :in             std_logic;\r
+       R_HFn                   :in             std_logic;\r
+       R_FFn                   :in             std_logic;\r
+       FLAG_IN_4       :in             std_logic;\r
+       S_EFn                   :in             std_logic;\r
+       S_HFn                   :in             std_logic;\r
+       S_FFn                   :in             std_logic;\r
+       HOLD                    :in             std_logic;\r
+       SYNC_FLAG       :out    std_logic_vector (7 downto 0)\r
+       );      \r
+end entity FLAG_BUS;\r
+\r
+architecture FLAG_BUS_DESIGN of FLAG_BUS is\r
+\r
+\r
+signal FF1_S_EFn       :std_logic;     \r
+signal FF1_S_HFn       :std_logic;\r
+signal FF1_S_FFn       :std_logic;\r
+signal FF1_R_EFn       :std_logic;\r
+signal FF1_R_HFn       :std_logic;\r
+signal FF1_R_FFn       :std_logic;\r
+\r
+signal FF2_S_EFn       :std_logic;     \r
+signal FF2_S_HFn       :std_logic;\r
+signal FF2_S_FFn       :std_logic;\r
+signal FF2_R_EFn       :std_logic;\r
+signal FF2_R_HFn       :std_logic;\r
+signal FF2_R_FFn       :std_logic;\r
+\r
+begin\r
+\r
+\r
+       process (PCI_CLOCK) \r
+       begin \r
+               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then \r
+\r
+               FF1_S_EFn       <=      S_EFn;\r
+               FF1_S_HFn       <=      S_HFn;\r
+               FF1_S_FFn       <=      S_FFn;\r
+               FF1_R_EFn       <=      R_EFn;\r
+               FF1_R_HFn       <=      R_HFn;\r
+               FF1_R_FFn       <=      R_FFn;\r
+\r
+               end if;\r
+       end process;    \r
+\r
+\r
+       process (PCI_CLOCK) \r
+       begin \r
+               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then  \r
+\r
+                       if                      HOLD    =       '0'     then\r
+\r
+                                       FF2_S_EFn       <=      FF1_S_EFn;      \r
+                                       FF2_S_HFn       <=      FF1_S_HFn;\r
+                                       FF2_S_FFn       <=      FF1_S_FFn;\r
+                                       FF2_R_EFn       <=      FF1_R_EFn;\r
+                                       FF2_R_HFn       <=      FF1_R_HFn;\r
+                                       FF2_R_FFn       <=      FF1_R_FFn;\r
+\r
+                               elsif   HOLD    =       '1'     then\r
+\r
+                                       FF2_S_EFn       <=      FF2_S_EFn;      \r
+                                       FF2_S_HFn       <=      FF2_S_HFn;\r
+                                       FF2_S_FFn       <=      FF2_S_FFn;\r
+                                       FF2_R_EFn       <=      FF2_R_EFn;\r
+                                       FF2_R_HFn       <=      FF2_R_HFn;\r
+                                       FF2_R_FFn       <=      FF2_R_FFn;\r
+\r
+                       end if;\r
+               end if;\r
+       end process;    \r
+\r
+       SYNC_FLAG(0)    <=      FLAG_IN_0;              \r
+       SYNC_FLAG(1)    <=      FF2_R_EFn;      \r
+       SYNC_FLAG(2)    <=      FF2_R_HFn;\r
+       SYNC_FLAG(3)    <=      FF2_R_FFn;\r
+       SYNC_FLAG(4)    <=      FLAG_IN_4;              \r
+       SYNC_FLAG(5)    <=      FF2_S_EFn;      \r
+       SYNC_FLAG(6)    <=      FF2_S_HFn;\r
+       SYNC_FLAG(7)    <=      FF2_S_FFn;\r
+\r
+end architecture FLAG_BUS_DESIGN;\r
+\r
diff --git a/dhwk/source/INTERRUPT.vhd b/dhwk/source/INTERRUPT.vhd
new file mode 100644 (file)
index 0000000..96ab264
--- /dev/null
@@ -0,0 +1,147 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: INTERRUPT.VHD\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+\r
+entity INTERRUPT is\r
+       port\r
+       (\r
+       PCI_CLOCK               :in             std_logic;\r
+       PCI_RSTn                :in     std_logic; -- PCI reset is asynchron (low active)\r
+       RESET                           :in     std_logic;\r
+       TAST_SETn               :in     std_logic;\r
+       TAST_RESn               :in     std_logic;\r
+       INT_IN_0                :in             std_logic;\r
+       INT_IN_1                :in             std_logic;\r
+       INT_IN_2                :in             std_logic;\r
+       INT_IN_3                :in             std_logic;\r
+       INT_IN_4                :in             std_logic;\r
+       INT_IN_5                :in             std_logic;\r
+       INT_IN_6                :in             std_logic;\r
+       INT_IN_7                :in             std_logic;\r
+       TRDYn                           :in     std_logic;  -- event 1 after read of Interrupt status register (low active)\r
+       READ_XX5_4      :in     std_logic;      -- event 2 after read of Interrupt status register\r
+       INT_RES                 :in             std_logic_vector(7 downto 0); -- clear selected interrupts\r
+       INT_MASKE               :in             std_logic_vector(7 downto 0);   -- interrupt mask register\r
+       INT_REG                 :out    std_logic_vector(7 downto 0); -- interrupt status register\r
+       INTAn                           :out    std_logic;      -- second interrupt line for PCI analyzer\r
+       PCI_INTAn               :out    std_logic               -- PCI interrupt line \r
+       );\r
+\r
+end entity INTERRUPT;\r
+\r
+architecture INTERRUPT_DESIGN of INTERRUPT is\r
+\r
+       signal  SIG_TAST_Q              :std_logic;\r
+       signal  SIG_TAST_Qn             :std_logic;\r
+\r
+\r
+       signal  SIG_INTA                        :std_logic; \r
+\r
+       signal FF_A                     :std_logic_vector(7 downto 0);\r
+       signal FF_B                     :std_logic_vector(7 downto 0);  \r
+       signal SET                      :std_logic_vector(7 downto 0);  \r
+\r
+       signal  SIG_PROPAGATE_INT :std_logic;\r
+       signal  SIG_PROPAGATE_INT_SECOND :std_logic;\r
+       signal  REG :std_logic_vector(7 downto 0);\r
+\r
+begin\r
+\r
+\r
+\r
+\r
+------------------------------------------------------\r
+       process (PCI_CLOCK) \r
+       begin \r
+               if  (PCI_CLOCK'event and PCI_CLOCK ='1')  then  \r
+\r
+                       SIG_TAST_Q              <= not (TAST_SETn and SIG_TAST_Qn);\r
+                       \r
+                       SIG_TAST_Qn             <= not (TAST_RESn and SIG_TAST_Q);\r
+       \r
+               end if;\r
+       end process;    \r
+\r
+------------------------------------------------------\r
+\r
+       process (PCI_CLOCK)\r
+       begin\r
+    if (PCI_RSTn = '0') then\r
+                                       SET <= "00000000";\r
+          FF_A <= "00000000";\r
+          FF_B <= "00000000";\r
+\r
+               elsif(PCI_CLOCK'event   and     PCI_CLOCK       =       '1')    then\r
+               if(RESET = '1') then\r
+                                               SET <= "00000000";\r
+            FF_A       <= "00000000";\r
+            FF_B       <= "00000000";\r
+      else     \r
+\r
+                       FF_A(0) <=                      INT_IN_0 ;  -- Receive FIFO Empty Flag\r
+\r
+                       FF_A(1) <=                      INT_IN_1 ;  -- Send FIFO Half Full\r
+                       FF_A(2) <=                      INT_IN_2 ; \r
+                       FF_A(3) <=                      INT_IN_3 ; \r
+\r
+                       FF_A(4) <=                      INT_IN_4 ; \r
+\r
+                       FF_A(5) <=                      INT_IN_5 ; \r
+                       FF_A(6) <=                      INT_IN_6 ; \r
+                       FF_A(7) <=                      INT_IN_7 ; \r
+\r
+                       FF_B    <= FF_A ;\r
+\r
+                       SET <= FF_A AND not FF_B;\r
+               end if;\r
+               end if;\r
+       end process;\r
+\r
+       process (PCI_CLOCK,PCI_RSTn)\r
+       begin\r
+               if (PCI_RSTn = '0') then\r
+                       REG <= "00000000";\r
+\r
+               elsif(PCI_CLOCK'event   and     PCI_CLOCK       =       '1')    then\r
+                               if(RESET = '1') then\r
+                                       REG <= "00000000";\r
+\r
+               elsif(SIG_TAST_Q = '1') then\r
+                       REG <= "00000000" or SET;\r
+\r
+        elsif (TRDYn = '0' AND READ_XX5_4 = '1') then\r
+            REG <= (REG AND NOT INT_RES) OR SET;\r
+        else\r
+            REG <= REG OR SET;\r
+        end if;\r
+    end if;\r
+       end process;\r
+\r
+       SIG_PROPAGATE_INT <= SIG_TAST_Q \r
+            OR (REG(0) AND INT_MASKE(0)) \r
+            OR (REG(1) AND INT_MASKE(1))\r
+            OR (REG(2) AND INT_MASKE(2))\r
+            OR (REG(3) AND INT_MASKE(3))\r
+            OR (REG(4) AND INT_MASKE(4))\r
+            OR (REG(5) AND INT_MASKE(5))\r
+            OR (REG(6) AND INT_MASKE(6))\r
+            OR (REG(7) AND INT_MASKE(7));\r
+\r
+       process (PCI_CLOCK)\r
+       begin\r
+               if(PCI_CLOCK'event      and     PCI_CLOCK       =       '1')    then\r
+       SIG_PROPAGATE_INT_SECOND        <= not SIG_PROPAGATE_INT;\r
+    end if;\r
+  end process;\r
+\r
+\r
+         INTAn <= not SIG_PROPAGATE_INT_SECOND;\r
+       PCI_INTAn       <= '0'  when SIG_PROPAGATE_INT_SECOND = '0'     else    'Z';\r
+\r
+       INT_REG <= REG;\r
+\r
+end architecture INTERRUPT_DESIGN;\r
diff --git a/dhwk/source/IO_RW_SEL.vhd b/dhwk/source/IO_RW_SEL.vhd
new file mode 100644 (file)
index 0000000..44419d8
--- /dev/null
@@ -0,0 +1,54 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: CONFIG_WR_SEL.VHD\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity IO_WR_SEL is\r
+       port\r
+       (\r
+       IO_WR_COM               :in             std_logic;\r
+       IRDY_REGn               :in             std_logic;\r
+       TRDYn                           :in             std_logic;\r
+       ADDR_REG                :in             std_logic_vector(31 downto 0);\r
+       CBE_REGn                :in             std_logic_vector( 3 downto 0);\r
+       WRITE_XX1_0     :out    std_logic;\r
+       WRITE_XX3_2     :out    std_logic;\r
+       WRITE_XX5_4     :out    std_logic;\r
+       WRITE_XX7_6     :out    std_logic \r
+       );\r
+end entity IO_WR_SEL;\r
+\r
+--PCI Byte Enable \r
+--C/BE[3..0] gueltige Datenbits \r
+-------------------------------\r
+--     0000            AD 31..0\r
+--     1000            AD 23..0\r
+--     1100            AD 15..0\r
+--     1110            AD  7..0\r
+--     0011            AD 31..16\r
+\r
+architecture IO_WR_SEL_DESIGN of IO_WR_SEL is\r
+\r
+       signal  WR_ENA  :std_logic;\r
+       signal  ADDR            :std_logic_vector( 5 downto 0); \r
+\r
+begin\r
+\r
+               WR_ENA  <=      '1' when\r
+                                                                               IO_WR_COM = '1' and\r
+                                                                               IRDY_REGn       =       '0' and\r
+                                                                               TRDYn                   =       '0'     else    '0';\r
+\r
+\r
+               ADDR    <=       ADDR_REG(3) &  ADDR_REG(2)     &       CBE_REGn;\r
+\r
+\r
+               WRITE_XX1_0     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "001100"        else '0';        \r
+               WRITE_XX3_2     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "000011"        else '0';\r
+               WRITE_XX5_4     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "011100"        else '0';        \r
+               WRITE_XX7_6     <=      '1'     when    WR_ENA  =       '1'     and     ADDR    =       "010011"        else '0';\r
+       \r
+end architecture IO_WR_SEL_DESIGN;\r
diff --git a/dhwk/source/Io_mux.vhd b/dhwk/source/Io_mux.vhd
new file mode 100644 (file)
index 0000000..ba27f4a
--- /dev/null
@@ -0,0 +1,36 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: IO_MUX.VHD\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity IO_MUX is\r
+       port\r
+       (\r
+       READ_SEL                        :in             std_logic_vector ( 1 downto 0);\r
+       USER_DATA                       :in             std_logic_vector (31 downto 0);\r
+       CONFIG_DATA             :in             std_logic_vector (31 downto 0);\r
+       PCI_AD                          :in             std_logic_vector (31 downto 0);\r
+       IO_DATA                         :out    std_logic_vector (31 downto 0)\r
+       );\r
+end entity IO_MUX;\r
+\r
+architecture IO_MUX_DESIGN of IO_MUX is\r
+\r
+       signal  MUX             :std_logic_vector (31 downto 0); \r
+\r
+begin \r
+\r
+       MUX     <=      PCI_AD                  when    READ_SEL        =       "00"    else    -- WRITE_CONFIG \r
+                                       PCI_AD                  when    READ_SEL        =       "01"    else    -- WRITE_IO\r
+                                       CONFIG_DATA     when    READ_SEL        =       "10"    else    -- READ_CONFIG \r
+                                       USER_DATA               when    READ_SEL        =       "11"    else    -- READ_IO      \r
+                                       CONFIG_DATA;\r
+\r
+--                                     MUX;\r
+\r
+       IO_DATA <= MUX;\r
+\r
+end architecture IO_MUX_DESIGN;\r
diff --git a/dhwk/source/Io_reg.vhd b/dhwk/source/Io_reg.vhd
new file mode 100644 (file)
index 0000000..f56df31
--- /dev/null
@@ -0,0 +1,74 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: IO_MUX.VHD\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+\r
+entity IO_REG is\r
+    port\r
+       (\r
+       PCI_CLOCK               :in             std_logic;\r
+       PCI_RSTn                :in             std_logic;\r
+       PCI_FRAMEn      :in             std_logic;\r
+       PCI_IRDYn               :in             std_logic;\r
+       PCI_IDSEL               :in             std_logic;\r
+       PCI_PAR                 :in             std_logic;\r
+       PCI_CBEn                :in             std_logic_vector ( 3 downto 0);\r
+       OE_PCI_AD               :in             std_logic;\r
+       IO_DATA                 :in             std_logic_vector (31 downto 0);\r
+       AD_REG                  :out    std_logic_vector (31 downto 0);\r
+       CBE_REGn                :out    std_logic_vector ( 3 downto 0);\r
+       FRAME_REGn      :out    std_logic;      \r
+       IRDY_REGn               :out    std_logic;      \r
+       IDSEL_REG               :out    std_logic;\r
+       PAR_REG                 :out    std_logic;              \r
+       PCI_AD                  :out    std_logic_vector (31 downto 0)  --      t/s\r
+    );\r
+end entity IO_REG;\r
+\r
+architecture IO_REG_DESIGN of IO_REG is\r
+\r
+       signal  REG_AD                  :std_logic_vector (31 downto 0); \r
+       signal  REG_CBEn                :std_logic_vector ( 3 downto 0);\r
+       signal  REG_FRAMEn      :std_logic;\r
+       signal  REG_IRDYn               :std_logic;\r
+       signal  REG_IDSEL               :std_logic;\r
+       signal  REG_PAR                 :std_logic;\r
+\r
+begin \r
+\r
+       process (PCI_CLOCK, PCI_RSTn) \r
+       begin\r
+               if      PCI_RSTn = '0'  then\r
+\r
+                       REG_AD                  <= X"00000000";\r
+                       REG_CBEn                <= "0000";\r
+                       REG_FRAMEn      <= '1';\r
+                       REG_IRDYn               <= '1';\r
+                       REG_IDSEL               <= '0';\r
+                       REG_PAR                 <= '0';\r
+\r
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
+\r
+                       REG_AD                  <=      IO_DATA;\r
+                       REG_CBEn                <=      PCI_CBEn;\r
+                       REG_FRAMEn      <=      PCI_FRAMEn;\r
+                       REG_IRDYn               <=      PCI_IRDYn;\r
+                       REG_IDSEL               <=      PCI_IDSEL;\r
+                       REG_PAR                 <=      PCI_PAR;\r
+\r
+               end if;\r
+       end process;\r
+\r
+       PCI_AD                  <=      REG_AD when OE_PCI_AD ='1' else (others => 'Z');\r
+\r
+       AD_REG                  <=      REG_AD;\r
+       CBE_REGn                <=      REG_CBEn;\r
+       FRAME_REGn      <=      REG_FRAMEn;\r
+       IRDY_REGn               <=      REG_IRDYn;\r
+       IDSEL_REG               <=      REG_IDSEL;\r
+       PAR_REG                 <=      REG_PAR;\r
+\r
+end architecture IO_REG_DESIGN;\r
diff --git a/dhwk/source/MESS_1_TB.vhd b/dhwk/source/MESS_1_TB.vhd
new file mode 100644 (file)
index 0000000..dbe1f78
--- /dev/null
@@ -0,0 +1,33 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 29.08.2006\r
+-- File: MESS_1_TB.VHD\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity MESS_1_TB is\r
+       port\r
+       (\r
+       KONST_1                         :in             std_logic;\r
+       PCI_IDSEL                       :in             std_logic;\r
+       DEVSELn                         :in             std_logic;\r
+       INTAn                                   :in             std_logic;\r
+       REG_OUT_XX7             :in             std_logic_vector(7 downto 0);\r
+       TB_PCI_IDSEL    :out    std_logic;\r
+       TB_DEVSELn              :out    std_logic;\r
+       TB_INTAn                        :out    std_logic\r
+       );\r
+end entity MESS_1_TB;\r
+\r
+architecture MESS_1_TB_DESIGN of MESS_1_TB is\r
\r
+begin\r
+\r
+       TB_PCI_IDSEL    <=      PCI_IDSEL       and     KONST_1;\r
+\r
+       TB_INTAn                        <=      INTAn                   and     KONST_1;                \r
+        \r
+       TB_DEVSELn              <=      DEVSELn when REG_OUT_XX7(7) = '0' else (not REG_OUT_XX7(6));\r
+\r
+end architecture MESS_1_TB_DESIGN;\r
diff --git a/dhwk/source/PAR_SER_CON.vhd b/dhwk/source/PAR_SER_CON.vhd
new file mode 100644 (file)
index 0000000..38300b7
--- /dev/null
@@ -0,0 +1,121 @@
+-- $Id: PAR_SER_CON.vhd,v 1.1 2007-03-10 11:24:03 sithglan Exp $\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+entity PAR_SER_CON     is\r
+       port\r
+       (\r
+       PCI_CLOCK               :in     std_logic; \r
+       RESET                           :in     std_logic; \r
+       PSC_ENABLE                      :in     std_logic; -- Parallel Serial Converter Enable\r
+       SYNC_S_FIFO_EFn                 :in     std_logic; -- Empty Flag (low active)\r
+       SPC_RDY_IN                      :in     std_logic; -- Ready to receive data\r
+       PAR_IN                          :in     std_logic_vector(7 downto 0);\r
+       SER_OUT                         :out    std_logic; -- Serial Output\r
+       S_FIFO_READn                    :out    std_logic  -- FIFO Read (low active)\r
+       );                      \r
+end entity     PAR_SER_CON ;\r
+\r
+architecture PAR_SER_CON_DESIGN        of PAR_SER_CON is\r
+\r
+constant STATE_END        :std_logic_vector(3 downto 0) := "0001";\r
+constant STATE_SEND       :std_logic_vector(3 downto 0) := "0010";\r
+constant STATE_SEND_BIT_0 :std_logic_vector(3 downto 0) := "0011";\r
+constant STATE_SEND_BIT_1 :std_logic_vector(3 downto 0) := "0100";\r
+constant STATE_SEND_BIT_2 :std_logic_vector(3 downto 0) := "0101";\r
+constant STATE_SEND_BIT_3 :std_logic_vector(3 downto 0) := "0110";\r
+constant STATE_SEND_BIT_4 :std_logic_vector(3 downto 0) := "0111";\r
+constant STATE_SEND_BIT_5 :std_logic_vector(3 downto 0) := "1000";\r
+constant STATE_SEND_BIT_6 :std_logic_vector(3 downto 0) := "1001";\r
+constant STATE_SEND_BIT_7 :std_logic_vector(3 downto 0) := "1010";\r
+\r
+signal COUNT     :std_logic_vector (3 downto 0);\r
+signal STATE     :std_logic_vector (3 downto 0); \r
+signal DATUM     :std_logic_vector (7 downto 0);\r
+signal SYNC                     :std_logic; -- make SPC_RDY_IN stable\r
+\r
+attribute syn_state_machine:boolean;\r
+attribute syn_state_machine of STATE: signal is false;\r
+attribute syn_state_machine of COUNT: signal is false;\r
+begin\r
+\r
+process(PCI_CLOCK)\r
+begin\r
+        if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
+                                       if ("0000" < COUNT) then\r
+                                               COUNT <= COUNT - 1;\r
+                                       end if;\r
+\r
+                if (RESET = '1') then\r
+                        STATE <= STATE_SEND;\r
+                        COUNT <= "0000";\r
+                        SER_OUT <= '0';\r
+                        S_FIFO_READn <= '1';\r
+\r
+                elsif (PSC_ENABLE = '1') then\r
+                                                                                               if (COUNT = "0000") then\r
+                        COUNT <= "0011";\r
+                        case STATE is\r
+                                when STATE_SEND =>\r
+                                        if(SYNC = '1' and SYNC_S_FIFO_EFn = '1') then\r
+                                                SER_OUT <= '1';\r
+                                                S_FIFO_READn <= '0';\r
+                                                STATE <= STATE_SEND_BIT_0;\r
+                                        end if;\r
+\r
+                                when STATE_SEND_BIT_0 =>\r
+                                                DATUM     <= PAR_IN;\r
+                                                S_FIFO_READn <= '1';\r
+                                                SER_OUT <= PAR_IN(0); \r
+                                                STATE <= STATE_SEND_BIT_1;\r
+                                  \r
+                                when STATE_SEND_BIT_1 =>\r
+                                        SER_OUT <= DATUM(1); \r
+                                        STATE <= STATE_SEND_BIT_2;\r
+\r
+                                when STATE_SEND_BIT_2 =>\r
+                                        SER_OUT <= DATUM(2); \r
+                                        STATE <= STATE_SEND_BIT_3;\r
+\r
+                                when STATE_SEND_BIT_3 =>\r
+                                        SER_OUT <= DATUM(3); \r
+                                        STATE <= STATE_SEND_BIT_4;\r
+\r
+                                when STATE_SEND_BIT_4 =>\r
+                                        SER_OUT <= DATUM(4); \r
+                                        STATE <= STATE_SEND_BIT_5;\r
+                                        \r
+                                when STATE_SEND_BIT_5 =>\r
+                                        SER_OUT <= DATUM(5); \r
+                                        STATE <= STATE_SEND_BIT_6;\r
+\r
+                                when STATE_SEND_BIT_6 =>\r
+                                        SER_OUT <= DATUM(6); \r
+                                        STATE <= STATE_SEND_BIT_7;\r
+                                        \r
+                                when STATE_SEND_BIT_7 =>\r
+                                        SER_OUT <= DATUM(7); \r
+                                        STATE <= STATE_END;\r
+\r
+                                when STATE_END =>\r
+                                        SER_OUT <= '0';\r
+                                        STATE <= STATE_SEND;\r
+\r
+                                when others => STATE <= STATE_END;\r
+                        end case;\r
+                    end if; -- COUNT\r
+                end if; -- RESET ... / PSC_ENABLE ...\r
+        end if; -- PCI_CLOCK ...\r
+end process;\r
+\r
+process(PCI_CLOCK)\r
+begin\r
+        if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
+                                               SYNC <= SPC_RDY_IN;\r
+                               end if;\r
+end process;\r
+\r
+\r
+end architecture PAR_SER_CON_DESIGN;\r
diff --git a/dhwk/source/Parity_4.vhd b/dhwk/source/Parity_4.vhd
new file mode 100644 (file)
index 0000000..7688160
--- /dev/null
@@ -0,0 +1,23 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: PARITY_4.VHD\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+\r
+entity PARITY_4 is\r
+       port\r
+       (\r
+       PAR_IN  :in             std_logic_vector(3 downto 0);   \r
+       PAR_OUT :out    std_logic\r
+       );\r
+end entity PARITY_4 ; \r
+\r
+architecture PARITY_4_DESIGN of PARITY_4 is\r
+\r
+begin\r
+\r
+       PAR_OUT <= PAR_IN(3) xor PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) ;\r
+\r
+end architecture PARITY_4_DESIGN;\r
diff --git a/dhwk/source/REG.vhd b/dhwk/source/REG.vhd
new file mode 100644 (file)
index 0000000..0c91d25
--- /dev/null
@@ -0,0 +1,38 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: REG.VHD\r
+\r
+library ieee ;\r
+use ieee.std_logic_1164.all ;\r
+\r
+entity REG is\r
+       port\r
+       (\r
+       CLOCK           :in             std_logic; \r
+       RESET           :in             std_logic; \r
+       WRITE           :in             std_logic;   \r
+       REG_IN  :in             std_logic_vector(7 downto 0);\r
+       REG_OUT :out    std_logic_vector(7 downto 0) \r
+       );\r
+end entity REG ;\r
+\r
+architecture REG_DESIGN of REG is\r
+\r
+       signal SIG_REG  :std_logic_vector (7 downto 0);\r
+\r
+begin\r
+\r
+       process (CLOCK) \r
+       begin\r
+               if (CLOCK'event and CLOCK = '1') then\r
+                       if                      RESET   =       '1'     then    SIG_REG <= X"00";\r
+                               elsif   WRITE   =       '1'     then    SIG_REG <= REG_IN;\r
+                               else                                                                            SIG_REG <= SIG_REG;\r
+               end if;\r
+               end if;\r
+       end process;\r
+\r
+       REG_OUT <= SIG_REG;\r
+\r
+end architecture REG_DESIGN;\r
diff --git a/dhwk/source/SER_PAR_CON.vhd b/dhwk/source/SER_PAR_CON.vhd
new file mode 100644 (file)
index 0000000..a030eaa
--- /dev/null
@@ -0,0 +1,154 @@
+-- $Id: SER_PAR_CON.vhd,v 1.1 2007-03-10 11:24:03 sithglan Exp $\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+entity SER_PAR_CON is\r
+       port\r
+       (\r
+       PCI_CLOCK                       :in     std_logic; \r
+       RESET                           :in     std_logic; \r
+       SPC_ENABLE                      :in     std_logic; -- Driver Enable Sender/Receiver\r
+       SYNC_R_FIFO_FFn                 :in     std_logic; -- FIFO Full Flag (low active)\r
+       SERIAL_IN                       :in     std_logic; -- Serial Input\r
+       R_FIFO_WRITEn                   :out    std_logic; -- FIFO Write (low active)\r
+       SPC_RDY_OUT                     :out    std_logic; -- Ready to Receive Data\r
+       PAR_OUT                         :out    std_logic_vector(7 downto 0)\r
+       );\r
+end entity SER_PAR_CON ;\r
+\r
+\r
+architecture SER_PAR_CON_DESIGN of SER_PAR_CON is\r
+\r
+-- constant STATE_RECV            :std_logic_vector(3 downto 0) := "0001";\r
+constant STATE_RECV_START_BIT  :std_logic_vector(3 downto 0) := "0010";\r
+constant STATE_RECV_BIT_0      :std_logic_vector(3 downto 0) := "0011";\r
+constant STATE_RECV_BIT_1      :std_logic_vector(3 downto 0) := "0100";\r
+constant STATE_RECV_BIT_2      :std_logic_vector(3 downto 0) := "0101";\r
+constant STATE_RECV_BIT_3      :std_logic_vector(3 downto 0) := "0110";\r
+constant STATE_RECV_BIT_4      :std_logic_vector(3 downto 0) := "0111";\r
+constant STATE_RECV_BIT_5      :std_logic_vector(3 downto 0) := "1000";\r
+constant STATE_RECV_BIT_6      :std_logic_vector(3 downto 0) := "1001";\r
+constant STATE_RECV_BIT_7      :std_logic_vector(3 downto 0) := "1010";\r
+constant STATE_RECV_FIFOFULL   :std_logic_vector(3 downto 0) := "1011";\r
+\r
+signal COUNT     :std_logic_vector (3 downto 0);\r
+signal STATE     :std_logic_vector (3 downto 0);\r
+signal STARTBIT  :std_logic_vector (3 downto 0);\r
+\r
+\r
+attribute syn_state_machine:boolean;\r
+attribute syn_state_machine of STATE: signal is false;\r
+attribute syn_state_machine of COUNT: signal is false;\r
+\r
+begin\r
+\r
+process(PCI_CLOCK)\r
+begin\r
+        if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
+                                               if ("0000" < COUNT) then\r
+                                               COUNT <= COUNT - 1;\r
+                                       end if;\r
+\r
+-- war nicht das Problem des Datenverlusts\r
+--        if (R_FIFO_WRITEn = '0' and COUNT = "0000") then\r
+--            R_FIFO_WRITEn <= '1';\r
+---      end if;\r
+\r
+                if (RESET = '1') then\r
+                        STATE <= STATE_RECV_START_BIT;\r
+                        COUNT <= "0000";\r
+                        R_FIFO_WRITEn <= '1';\r
+\r
+                elsif (SPC_ENABLE = '1') then\r
+                       \r
+                                                                                        if (STATE = STATE_RECV_START_BIT) then\r
+                              R_FIFO_WRITEn <= '1';\r
+                                                                                               if (STARTBIT = "0011") then\r
+                                                                                                                               COUNT <= "0011";\r
+                                   STATE <= STATE_RECV_BIT_0;\r
+                              end if;\r
+\r
+                       elsif (STATE = STATE_RECV_FIFOFULL) then\r
+                              if (SYNC_R_FIFO_FFn = '1') then\r
+                                      R_FIFO_WRITEn <= '0';\r
+                                      STATE <= STATE_RECV_START_BIT;\r
+                              end if;\r
+\r
+                       elsif (COUNT = "0000") then\r
+                        COUNT <= "0011";\r
+                        case STATE is\r
+                                                                                                                               \r
+                                when STATE_RECV_BIT_0 =>\r
+                                        PAR_OUT(0) <= STARTBIT(0);\r
+                                        STATE <= STATE_RECV_BIT_1;\r
+\r
+                                when STATE_RECV_BIT_1 =>\r
+                                        PAR_OUT(1) <= STARTBIT(0);\r
+                                        STATE <= STATE_RECV_BIT_2;\r
+                                        \r
+                                when STATE_RECV_BIT_2 =>\r
+                                        PAR_OUT(2) <= STARTBIT(0);\r
+                                        STATE <= STATE_RECV_BIT_3;\r
+                                        \r
+                                when STATE_RECV_BIT_3 =>\r
+                                        PAR_OUT(3) <= STARTBIT(0);\r
+                                        STATE <= STATE_RECV_BIT_4;\r
+                                        \r
+                                when STATE_RECV_BIT_4 =>\r
+                                        PAR_OUT(4) <= STARTBIT(0);\r
+                                        STATE <= STATE_RECV_BIT_5;\r
+                                        \r
+                                when STATE_RECV_BIT_5 =>\r
+                                        PAR_OUT(5) <= STARTBIT(0);\r
+                                        STATE <= STATE_RECV_BIT_6;\r
+                                        \r
+                                when STATE_RECV_BIT_6 =>\r
+                                        PAR_OUT(6) <= STARTBIT(0);\r
+                                        STATE <= STATE_RECV_BIT_7;\r
+                                        \r
+                                when STATE_RECV_BIT_7 =>\r
+                                        PAR_OUT(7) <= STARTBIT(0);\r
+\r
+                                        if (SYNC_R_FIFO_FFn = '1') then\r
+                                             STATE <= STATE_RECV_START_BIT;\r
+                                             R_FIFO_WRITEn <= '0';\r
+                                        else \r
+                                             STATE <= STATE_RECV_FIFOFULL;\r
+                                        end if;\r
+\r
+                                                                                                                               when others =>\r
+                                                                                                                                                               STATE <= STATE_RECV_START_BIT;\r
+\r
+                        end case;\r
+                     end if; -- COUNT\r
+                end if; -- RESET ... / SPC_ENABLE ...\r
+        end if; -- PCI_CLOCK ...\r
+end process;\r
+\r
+process(PCI_CLOCK)\r
+begin\r
+               if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
+      SPC_RDY_OUT <= SPC_ENABLE AND SYNC_R_FIFO_FFn;\r
+               end if;\r
+end process;\r
+\r
+\r
+process(PCI_CLOCK)\r
+begin\r
+        if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
+                                       if (RESET = '1') then\r
+                                               STARTBIT <= "0000";\r
+                                       else\r
+                                       STARTBIT(0) <= SERIAL_IN;\r
+                                       STARTBIT(1) <= STARTBIT(0);\r
+                                       STARTBIT(2) <= STARTBIT(1);\r
+                                       STARTBIT(3) <= STARTBIT(2);\r
+                                       end if;                           \r
+                       end if;\r
+end process;\r
+\r
+\r
+\r
+end architecture SER_PAR_CON_DESIGN;\r
diff --git a/dhwk/source/Verg_2.vhd b/dhwk/source/Verg_2.vhd
new file mode 100644 (file)
index 0000000..39d51ac
--- /dev/null
@@ -0,0 +1,31 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: VERG_2.VHD\r
+\r
+library ieee ;\r
+use ieee.std_logic_1164.all ;\r
+\r
+entity VERG_2  is\r
+       port\r
+       (\r
+       IN_A            :in             std_logic_vector(1 downto 0);\r
+       IN_B            :in             std_logic_vector(1 downto 0);\r
+       GLEICH  :out    std_logic\r
+       );\r
+end entity VERG_2 ;\r
+\r
+architecture VERG_2_DESIGN of VERG_2 is\r
+\r
+begin\r
+\r
+       process (IN_A,IN_B) \r
+       begin \r
+\r
+               if                      IN_A    =       IN_B    then    GLEICH  <=      '1';\r
+                       else                                                                                    GLEICH  <=      '0';   \r
+               end if;\r
+\r
+       end process;\r
+\r
+end architecture VERG_2_DESIGN ;\r
diff --git a/dhwk/source/Verg_4.vhd b/dhwk/source/Verg_4.vhd
new file mode 100644 (file)
index 0000000..6aafdad
--- /dev/null
@@ -0,0 +1,32 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: VERG_4.VHD\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+\r
+entity VERG_4 is\r
+       port\r
+       (\r
+       IN_A            :in             std_logic_vector(3 downto 0);\r
+       IN_B            :in             std_logic_vector(3 downto 0);\r
+       GLEICH  :out    std_logic\r
+       );\r
+end entity VERG_4 ;\r
+\r
+architecture VERG_4_DESIGN of VERG_4 is\r
+\r
+begin\r
+\r
+       process (IN_A,IN_B) \r
+       begin \r
+\r
+               if                      IN_A    =       IN_B    then    GLEICH  <=      '1';\r
+                       else                                                                                    GLEICH  <=      '0';   \r
+               end if;\r
+\r
+       end process;\r
+\r
+end architecture VERG_4_DESIGN;\r
+\r
diff --git a/dhwk/source/config_00h.vhd b/dhwk/source/config_00h.vhd
new file mode 100644 (file)
index 0000000..0346aeb
--- /dev/null
@@ -0,0 +1,28 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: CONFIG_00H.VHD\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity CONFIG_00H is\r
+       port\r
+       (\r
+       VENDOR_ID                       :in             std_logic_vector (15 downto 0);\r
+       CONF_DATA_00H   :out    std_logic_vector (31 downto 0)\r
+       );\r
+end entity CONFIG_00H;\r
+\r
+architecture CONFIG_00H_DESIGN of CONFIG_00H is\r
+\r
+-- PCI Configuration Space Header Addr : HEX 00 --\r
+\r
+       constant        CONF_DEVICE_ID          :std_logic_vector(31 downto 16) := X"AFFE";--???? \r
+--constant     CONF_VENDOR_ID          :std_logic_vector(15 downto  0) := X"BAFF";--???? \r
+\r
+begin\r
+\r
+       CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;\r
+\r
+end architecture CONFIG_00H_DESIGN;\r
diff --git a/dhwk/source/config_04h.vhd b/dhwk/source/config_04h.vhd
new file mode 100644 (file)
index 0000000..2dbacf1
--- /dev/null
@@ -0,0 +1,115 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: CONFIG_04H.VHD\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity CONFIG_04H is\r
+       port\r
+       (\r
+       PCI_CLOCK                       :in             std_logic;\r
+       PCI_RSTn                        :in             std_logic;\r
+       SERR                                    :in             std_logic;\r
+       PERR                                    :in             std_logic;\r
+       AD_REG                          :in             std_logic_vector(31 downto 0);\r
+       CBE_REGn                        :in             std_logic_vector( 3 downto 0);\r
+       CONF_WR_04H             :in             std_logic;\r
+       CONF_DATA_04H   :out    std_logic_vector(31 downto 0)\r
+       );\r
+end entity CONFIG_04H;\r
+\r
+architecture CONFIG_04H_DESIGN of CONFIG_04H is\r
+\r
+       signal          CONF_STATUS             :std_logic_vector(31 downto 16);\r
+       signal          CONF_COMMAND    :std_logic_vector(15 downto  0);\r
+\r
+\r
+begin\r
+\r
+--*******************************************************************\r
+--************* PCI Configuration Space Header "STATUS" *************\r
+--*******************************************************************\r
+\r
+       CONF_STATUS(20 downto 16)       <= "00000"      ;-- Reserved\r
+       CONF_STATUS(21          )       <= '0'                  ;-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz\r
+       CONF_STATUS(22                                  )       <= '0'                  ;-- MAS/TAR: "R_O" \r
+       CONF_STATUS(23          )       <= '0'                  ;-- ???/???: "R_O" : fast back-to-back\r
+       CONF_STATUS(24          )       <= '0'                  ;-- Master :\r
+--CONF_STATUS(26 downto 25)    <= "00"                 ;-- Mas/Tar: "R_O" : timing fast   for "DEVSEL"\r
+       CONF_STATUS(26 downto 25)       <= "01"                 ;-- Mas/Tar: "R_O" : timing medium for "DEVSEL"\r
+--CONF_STATUS(26 downto 25)    <= "10"                 ;-- Mas/Tar: "R_O" : timing slow   for "DEVSEL"\r
+--CONF_STATUS(26 downto 25)    <= "11"                 ;-- Mas/Tar: "R_O" : reserved\r
+       CONF_STATUS(27          )       <= '0'                  ;-- Target : "R_W" : Taget-Abort\r
+       CONF_STATUS(28                                  )       <= '0'                  ;-- Master : "R_W" : Taget-Abort\r
+       CONF_STATUS(29          )       <= '0'                  ;-- Master : "R_W" : Master-Abort\r
+--CONF_STATUS(30                                       )       <= SERR                 ;-- Mas/Tar: "R_W" : SERR\r
+--CONF_STATUS(31                                       )       <= PERR                 ;-- Mas/Tar: "R_W" : PERR\r
+\r
+       process (PCI_CLOCK,PCI_RSTn) \r
+       begin\r
+               if PCI_RSTn = '0' then  CONF_STATUS(30) <= '0';\r
+                                                                                                               CONF_STATUS(31) <= '0';\r
+\r
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
+\r
+                       if                      CONF_WR_04H     = '1' and CBE_REGn(3) = '0' then \r
+\r
+                                                       CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30)); \r
+                                                       CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31));\r
+\r
+                               else    CONF_STATUS(30) <= SERR or CONF_STATUS(30);\r
+                                                       CONF_STATUS(31) <= PERR or CONF_STATUS(31);\r
+\r
+                       end if; \r
+               end if; \r
+       end process;\r
+\r
+--*******************************************************************\r
+--*********** PCI Configuration Space Header "COMMAND" **************\r
+--*******************************************************************\r
+\r
+--     CONF_COMMAND( 0) <= '0';-- I/O Space accesses ???\r
+--     CONF_COMMAND( 1) <= '0';-- Mem Space accesses ???\r
+--     CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus \r
+--     CONF_COMMAND( 3) <= '0';-- Special Cycle ???\r
+--     CONF_COMMAND( 4) <= '0';-- Master ??? \r
+--     CONF_COMMAND( 5) <= '0';-- VGA    ???\r
+--     CONF_COMMAND( 6) <= '0';-- Party checking enable/disable\r
+               CONF_COMMAND( 7) <= '0';-- address/data stepping ???\r
+--     CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn"\r
+--     CONF_COMMAND( 9) <= '0';-- fast back-to-back\r
+--     CONF_COMMAND(10) <= '0';-- Reserved\r
+--     CONF_COMMAND(11) <= '0';-- Reserved\r
+--     CONF_COMMAND(12) <= '0';-- Reserved\r
+--     CONF_COMMAND(13) <= '0';-- Reserved\r
+--     CONF_COMMAND(14) <= '0';-- Reserved\r
+--     CONF_COMMAND(15) <= '0';-- Reserved\r
+\r
+       process (PCI_CLOCK,PCI_RSTn) \r
+       begin\r
+               if PCI_RSTn = '0' then  CONF_COMMAND(15 downto 8) <= (others =>'0');\r
+                                                                                                               CONF_COMMAND( 6 downto 0) <= (others =>'0');\r
+\r
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
+\r
+                       if              CONF_WR_04H      = '1'and CBE_REGn(1) = '0' then \r
+\r
+                                                       CONF_COMMAND(15 downto 8)       <=                              AD_REG(15 downto 8);\r
+                               else    CONF_COMMAND(15 downto 8)       <=      CONF_COMMAND(15 downto 8);\r
+                       end if;\r
+\r
+\r
+                       if              CONF_WR_04H      = '1'and CBE_REGn(0) = '0' then \r
+\r
+                                                       CONF_COMMAND( 6 downto 0) <=                            AD_REG( 6 downto 0);\r
+                               else    CONF_COMMAND( 6 downto 0) <=    CONF_COMMAND( 6 downto 0);\r
+                       end if;\r
+\r
+               end if;\r
+       end process;\r
+\r
+       CONF_DATA_04H   <= CONF_STATUS & CONF_COMMAND;  \r
+\r
+end architecture CONFIG_04H_DESIGN;\r
diff --git a/dhwk/source/config_08h.vhd b/dhwk/source/config_08h.vhd
new file mode 100644 (file)
index 0000000..b400eab
--- /dev/null
@@ -0,0 +1,28 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: CONFIG_08H.VHD\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity CONFIG_08H is\r
+       port\r
+       (\r
+       REVISION_ID             :in             std_logic_vector ( 7 downto 0);\r
+       CONF_DATA_08H   :out    std_logic_vector (31 downto 0)\r
+       );\r
+end entity CONFIG_08H;\r
+\r
+architecture CONFIG_08H_DESIGN of CONFIG_08H is\r
+\r
+-- PCI Configuration Space Header Addr : HEX 08 --\r
+\r
+       constant        CONF_CLASS_CODE         :std_logic_vector (31 downto  8) := X"078000";--other comm. device              \r
+--constant     CONF_REVISION_ID        :std_logic_vector ( 7 downto  0) := X"00";                      \r
+\r
+begin\r
+\r
+       CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;\r
+\r
+end architecture CONFIG_08H_DESIGN;\r
diff --git a/dhwk/source/config_10h.vhd b/dhwk/source/config_10h.vhd
new file mode 100644 (file)
index 0000000..6621607
--- /dev/null
@@ -0,0 +1,87 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: CONFIG_10H.VHD\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity CONFIG_10H is\r
+       port\r
+       (\r
+       PCI_CLOCK                       :in             std_logic;\r
+       PCI_RSTn                        :in             std_logic;\r
+       AD_REG                          :in             std_logic_vector(31 downto 0);\r
+       CBE_REGn                        :in             std_logic_vector( 3 downto 0);\r
+       CONF_WR_10H             :in             std_logic;\r
+       CONF_DATA_10H   :out    std_logic_vector(31 downto 0)\r
+       );\r
+end entity CONFIG_10H;\r
+\r
+architecture CONFIG_10H_DESIGN of CONFIG_10H is\r
+\r
+       signal          CONF_BAS_ADDR_REG       :std_logic_vector(31 downto  0);\r
+\r
+begin\r
+\r
+--*******************************************************************\r
+--***** PCI Configuration Space Header "BASE ADDRESS REGISTER" ******\r
+--*******************************************************************\r
+\r
+       CONF_BAS_ADDR_REG(1 downto 0) <= "01"   ;-- Base Address Register for "I/O"\r
+       CONF_BAS_ADDR_REG(3 downto 2)   <= "00" ;-- IO Bereich = 16 BYTE\r
+\r
+       process (PCI_CLOCK,PCI_RSTn) \r
+       begin\r
+\r
+--     if PCI_RSTn = '0' then  CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0');\r
+               if PCI_RSTn = '0' then  CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0');\r
+                                                               \r
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
+\r
+                       if                      CONF_WR_10H      = '1'and CBE_REGn(3) = '0' then \r
+\r
+                                                       CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24);\r
+\r
+                               else    CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24);\r
+                       end if;\r
+\r
+                       if                      CONF_WR_10H      = '1'and CBE_REGn(2) = '0' then \r
+\r
+                                                       CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16);\r
+\r
+                               else    CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16);\r
+                       end if;\r
+\r
+                       if                      CONF_WR_10H      = '1'and CBE_REGn(1) = '0' then \r
+\r
+                                                       CONF_BAS_ADDR_REG(15 downto  8) <= AD_REG(15 downto  8);\r
+\r
+                               else    CONF_BAS_ADDR_REG(15 downto  8) <= CONF_BAS_ADDR_REG(15 downto  8);\r
+                       end if;\r
+\r
+--                     if                      CONF_WR_10H      = '1'and CBE_REGn(0) = '0' then \r
+--\r
+--                                                     CONF_BAS_ADDR_REG( 7 downto  2) <= AD_REG( 7 downto  2);\r
+--\r
+--                             else    CONF_BAS_ADDR_REG( 7 downto  2) <= CONF_BAS_ADDR_REG( 7 downto  2);\r
+--                     end if;\r
+\r
+                       if                      CONF_WR_10H      = '1'and CBE_REGn(0) = '0' then \r
+\r
+                                                       CONF_BAS_ADDR_REG( 7 downto  4) <= AD_REG( 7 downto  4);\r
+\r
+                               else    CONF_BAS_ADDR_REG( 7 downto  4) <= CONF_BAS_ADDR_REG( 7 downto  4);\r
+                       end if;\r
+\r
+\r
+               end if;\r
+\r
+       end process;\r
+\r
+       CONF_DATA_10H   <= CONF_BAS_ADDR_REG;\r
+\r
+end architecture CONFIG_10H_DESIGN;\r
+\r
+\r
+\r
diff --git a/dhwk/source/config_3Ch.vhd b/dhwk/source/config_3Ch.vhd
new file mode 100644 (file)
index 0000000..642a484
--- /dev/null
@@ -0,0 +1,66 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: CONFIG_3CH.VHD\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity CONFIG_3CH is\r
+    port\r
+       (\r
+       PCI_CLOCK                       :in             std_logic;\r
+       PCI_RSTn                        :in             std_logic;\r
+       AD_REG                          :in             std_logic_vector (31 downto 0);\r
+       CBE_REGn                        :in             std_logic_vector ( 3 downto 0);\r
+       CONF_WR_3CH             :in             std_logic;\r
+       CONF_DATA_3CH   :out    std_logic_vector (31 downto 0)\r
+    );\r
+end entity CONFIG_3CH;\r
+\r
+architecture CONFIG_3CH_DESIGN of CONFIG_3CH is\r
+\r
+-- PCI Configuration Space Header Addr : HEX 3C --\r
+\r
+       signal          CONF_MAX_LAT            :std_logic_vector (31 downto 24);\r
+       signal          CONF_MIN_GNT            :std_logic_vector (23 downto 16);  \r
+       signal          CONF_INT_PIN            :std_logic_vector (15 downto  8);\r
+       signal          CONF_INT_LINE           :std_logic_vector ( 7 downto  0);  \r
+\r
+begin \r
+\r
+--*******************************************************************\r
+--*********** PCI Configuration Space Header "INTERRUPT" ************\r
+--*******************************************************************\r
+\r
+               CONF_MAX_LAT    <= X"00";\r
+               CONF_MIN_GNT    <= X"00";\r
+--     CONF_INT_PIN    <= X"00";                               -- Interrupt -\r
+               CONF_INT_PIN    <= X"01";                               -- Interrupt A\r
+--     CONF_INT_PIN    <= X"02";                               -- Interrupt B\r
+--     CONF_INT_PIN    <= X"03";                               -- Interrupt C \r
+--     CONF_INT_PIN    <= X"04";                               -- Interrupt D\r
+--     CONF_INT_PIN    <= X"05 - FF0"; -- Reserviert\r
+\r
+       process (PCI_CLOCK,PCI_RSTn) \r
+       begin\r
+               if PCI_RSTn = '0' then  CONF_INT_LINE <= (others =>'0');\r
+       \r
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
+\r
+                       if                      CONF_WR_3CH      = '1'and CBE_REGn(0) = '0' then \r
+\r
+                                                       CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);\r
+                               else    CONF_INT_LINE(7 downto 0) <= CONF_INT_LINE(7 downto 0);\r
+                       end if;\r
+\r
+               end if;\r
+\r
+       end process;\r
+\r
+       CONF_DATA_3CH   <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE ;\r
+\r
+end architecture CONFIG_3CH_DESIGN;\r
+\r
+\r
+\r
diff --git a/dhwk/source/config_mux_0.vhd b/dhwk/source/config_mux_0.vhd
new file mode 100644 (file)
index 0000000..64e2560
--- /dev/null
@@ -0,0 +1,44 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: CONFIG_MUX_0.VHD\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity CONFIG_MUX_0 is\r
+       port\r
+       (\r
+       READ_SEL                        :in             std_logic_vector( 2 downto 0);\r
+       CONF_DATA_00H   :in             std_logic_vector(31 downto 0);\r
+       CONF_DATA_04H   :in             std_logic_vector(31 downto 0);\r
+       CONF_DATA_08H   :in             std_logic_vector(31 downto 0);\r
+       CONF_DATA_10H   :in             std_logic_vector(31 downto 0);\r
+       CONF_DATA_3CH   :in             std_logic_vector(31 downto 0);\r
+--CONF_DATA_40H        :in             std_logic_vector(31 downto 0);\r
+       CONF_DATA                       :out    std_logic_vector(31 downto 0)\r
+    );\r
+end entity CONFIG_MUX_0;\r
+\r
+architecture CONFIG_MUX_0_DESIGN of CONFIG_MUX_0 is\r
+\r
+       signal  MUX     :std_logic_vector (31 downto  0); \r
+\r
+begin\r
+\r
+--*******************************************************************\r
+--******************* PCI Read  Config-MUX **************************\r
+--*******************************************************************\r
+\r
+       MUX <=  CONF_DATA_00H   when READ_SEL <= "000" else \r
+                                       CONF_DATA_04H   when READ_SEL <= "001" else\r
+                                       CONF_DATA_08H   when READ_SEL <= "010" else\r
+                                       CONF_DATA_10H   when READ_SEL <= "011" else\r
+                                       CONF_DATA_3CH   when READ_SEL <= "100" else\r
+--                             CONF_DATA_40H   when READ_SEL <= "101" else\r
+                                       X"00000000"     ;\r
+\r
+       CONF_DATA <= MUX ;\r
+\r
+\r
+end architecture CONFIG_MUX_0_DESIGN;\r
diff --git a/dhwk/source/config_rd_0.vhd b/dhwk/source/config_rd_0.vhd
new file mode 100644 (file)
index 0000000..1b19b63
--- /dev/null
@@ -0,0 +1,122 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: CONFIG_RD_0.VHD\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity CONFIG_RD_0 is\r
+    port\r
+       (\r
+       ADDR_REG        :in             std_logic_vector (31 downto 0);\r
+       CF_RD_COM       :in             std_logic;\r
+       READ_SEL        :out    std_logic_vector ( 2 downto 0)\r
+    );\r
+end entity CONFIG_RD_0;\r
+\r
+architecture CONFIG_RD_0_DESIGN of CONFIG_RD_0 is\r
+\r
+--\r
+--\r
+--\r
+--\r
+--\r
+--                            PCI Configuration Space Header\r
+--\r
+--            \                        Bit\r
+--                        \\r
+--Address              |31               24|23           16|15            8|7             0|      \r
+-----------------------------------------------------------------\r
+--00                   |Device ID                              |Vendor ID                              |                                       \r
+--04                   |Status                                 |Command                                |\r
+--08                   |Class Code                                                     |Revision ID|\r
+--0C                   |BIST           |Header Type|Latency T. |Cache L.S.     |\r
+--10-24                        |Base Address Register                                                  |\r
+--28                   |Cardbus CIS Pointer                                                    |\r
+--2C                   |Subsystem ID                   |Subsystem Vendor ID    |\r
+--30                   |Expansion ROM Base Address                                             |\r
+--34                   |Reserved                                                                               |\r
+--38                   |Reserved                                                                               |\r
+--3C                   |Max_Lat        |Min_Gnt        |Int_Pin        |Int_Line       |\r
+--40-FF                        |                                                                                               |\r
+-----------------------------------------------------------------\r
+\r
+\r
+--PCI Bus Commands \r
+--C/BE[3..0] Command Type\r
+--------------------------------------\r
+--     0000            Interrupt Acknowledge\r
+--     0001            Special Cycle\r
+--     0010            I/O Read\r
+--     0011            I/O Write\r
+--     0100            Reserved\r
+--     0101            Reserved\r
+--     0110            Memory Read\r
+--     0111            Memory Write\r
+--\r
+--     1000            Reserved\r
+--     1001            Reserved\r
+--     1010            Configuration Read\r
+--     1011            Configuration Write\r
+--     1100            Memory Read Multiple \r
+--     1101            Dual Address Cycle\r
+--     1110            Memory Read Line\r
+--     1111            Memory Write and Invalidate\r
+\r
+\r
+--PCI Byte Enable \r
+--C/BE[3..0] gueltige Datenbits \r
+-------------------------------\r
+--     0000            AD 31..0\r
+--     1000            AD 23..0\r
+--     1100            AD 15..0\r
+--     1110            AD  7..0\r
+\r
+       constant        CMD_INT_ACK                     :std_logic_vector(3 downto 0) := "0000";\r
+       constant        CMD_SP_CYC                      :std_logic_vector(3 downto 0) := "0001";\r
+       constant        CMD_IO_READ                     :std_logic_vector(3 downto 0) := "0010";\r
+       constant        CMD_IO_WRITE            :std_logic_vector(3 downto 0) := "0011";\r
+       constant        CMD_RES_4                               :std_logic_vector(3 downto 0) := "0100";\r
+       constant        CMD_RES_5                               :std_logic_vector(3 downto 0) := "0101";\r
+       constant        CMD_MEM_READ            :std_logic_vector(3 downto 0) := "0110";\r
+       constant        CMD_MEM_WRITE           :std_logic_vector(3 downto 0) := "0111";\r
+       constant        CMD_RES_8                               :std_logic_vector(3 downto 0) := "1000";\r
+       constant        CMD_RES_9                               :std_logic_vector(3 downto 0) := "1001";\r
+       constant        CMD_CONF_READ           :std_logic_vector(3 downto 0) := "1010";\r
+       constant        CMD_CONF_WRITE  :std_logic_vector(3 downto 0) := "1011";\r
+       constant        CMD_MEM_READ_M  :std_logic_vector(3 downto 0) := "1100";\r
+       constant        CMD_DU_ADR_CYC  :std_logic_vector(3 downto 0) := "1101";\r
+       constant        CMD_MEN_READ_L  :std_logic_vector(3 downto 0) := "1110";\r
+       constant        CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";\r
+\r
+       signal          MUX                                                     :std_logic_vector(31 downto 0); \r
+       signal          CONFIG_ADDR                     :std_logic_vector( 7 downto 0); \r
+\r
+begin\r
+\r
+       CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);\r
+\r
+--*******************************************************************\r
+--*********************** PCI Read Address **************************\r
+--*******************************************************************\r
+\r
+       process (CF_RD_COM, CONFIG_ADDR) \r
+       begin\r
+\r
+               if      CF_RD_COM = '1' then\r
+\r
+                       if              CONFIG_ADDR = X"00"     then    READ_SEL <= "000";\r
+                       elsif   CONFIG_ADDR = X"04"     then    READ_SEL <= "001";\r
+                       elsif   CONFIG_ADDR = X"08"     then    READ_SEL <= "010";\r
+                       elsif   CONFIG_ADDR = X"10"     then    READ_SEL <= "011";\r
+                       elsif   CONFIG_ADDR = X"3C"     then    READ_SEL <= "100";\r
+                       elsif   CONFIG_ADDR = X"40"     then    READ_SEL <= "101";\r
+                       else                                                            READ_SEL <= "111";\r
+                       end if;\r
+               else                                                                    READ_SEL <= "111";\r
+               end if;\r
+       end process;\r
+\r
+end architecture CONFIG_RD_0_DESIGN;\r
+\r
diff --git a/dhwk/source/config_space_header.vhd b/dhwk/source/config_space_header.vhd
new file mode 100644 (file)
index 0000000..8f61602
--- /dev/null
@@ -0,0 +1,157 @@
+-- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007\r
+\r
+\r
+\r
+LIBRARY ieee;\r
+\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+\r
+entity CONFIG_SPACE_HEADER is\r
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
+             ADDR_REG : In    std_logic_vector (31 downto 0);\r
+             CBE_REGn : In    std_logic_vector (3 downto 0);\r
+             CF_RD_COM : In    std_logic;\r
+             CF_WR_COM : In    std_logic;\r
+             IRDY_REGn : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+                PERR : In    std_logic;\r
+             REVISION_ID : In    std_logic_vector (7 downto 0);\r
+                SERR : In    std_logic;\r
+               TRDYn : In    std_logic;\r
+             VENDOR_ID : In    std_logic_vector (15 downto 0);\r
+             CONF_DATA : Out   std_logic_vector (31 downto 0);\r
+             CONF_DATA_04H : Out   std_logic_vector (31 downto 0);\r
+             CONF_DATA_10H : Out   std_logic_vector (31 downto 0) );\r
+end CONFIG_SPACE_HEADER;\r
+\r
+architecture SCHEMATIC of CONFIG_SPACE_HEADER is\r
+\r
+   SIGNAL gnd : std_logic := '0';\r
+   SIGNAL vcc : std_logic := '1';\r
+\r
+   signal CONF_WR_04H : std_logic;\r
+   signal CONF_WR_10H : std_logic;\r
+   signal CONF_WR_3CH : std_logic;\r
+   signal CONF_READ_SEL : std_logic_vector (2 downto 0);\r
+   signal CONF_DATA_10H_DUMMY : std_logic_vector (31 downto 0);\r
+   signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);\r
+   signal CONF_DATA_3CH : std_logic_vector (31 downto 0);\r
+   signal CONF_DATA_08H : std_logic_vector (31 downto 0);\r
+   signal CONF_DATA_00H : std_logic_vector (31 downto 0);\r
+\r
+   component CONFIG_MUX_0\r
+      Port ( CONF_DATA_00H : In    std_logic_vector (31 downto 0);\r
+             CONF_DATA_04H : In    std_logic_vector (31 downto 0);\r
+             CONF_DATA_08H : In    std_logic_vector (31 downto 0);\r
+             CONF_DATA_10H : In    std_logic_vector (31 downto 0);\r
+             CONF_DATA_3CH : In    std_logic_vector (31 downto 0);\r
+             READ_SEL : In    std_logic_vector (2 downto 0);\r
+             CONF_DATA : Out   std_logic_vector (31 downto 0) );\r
+   end component;\r
+\r
+   component CONFIG_RD_0\r
+      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);\r
+             CF_RD_COM : In    std_logic;\r
+             READ_SEL : Out   std_logic_vector (2 downto 0) );\r
+   end component;\r
+\r
+   component CONFIG_WR_0\r
+      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);\r
+             CF_WR_COM : In    std_logic;\r
+             IRDY_REGn : In    std_logic;\r
+               TRDYn : In    std_logic;\r
+             CONF_WR_04H : Out   std_logic;\r
+             CONF_WR_10H : Out   std_logic;\r
+             CONF_WR_3CH : Out   std_logic );\r
+   end component;\r
+\r
+   component CONFIG_3CH\r
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
+             CBE_REGn : In    std_logic_vector (3 downto 0);\r
+             CONF_WR_3CH : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             CONF_DATA_3CH : Out   std_logic_vector (31 downto 0) );\r
+   end component;\r
+\r
+   component CONFIG_10H\r
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
+             CBE_REGn : In    std_logic_vector (3 downto 0);\r
+             CONF_WR_10H : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             CONF_DATA_10H : Out   std_logic_vector (31 downto 0) );\r
+   end component;\r
+\r
+   component CONFIG_08H\r
+      Port ( REVISION_ID : In    std_logic_vector (7 downto 0);\r
+             CONF_DATA_08H : Out   std_logic_vector (31 downto 0) );\r
+   end component;\r
+\r
+   component CONFIG_00H\r
+      Port ( VENDOR_ID : In    std_logic_vector (15 downto 0);\r
+             CONF_DATA_00H : Out   std_logic_vector (31 downto 0) );\r
+   end component;\r
+\r
+   component CONFIG_04H\r
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
+             CBE_REGn : In    std_logic_vector (3 downto 0);\r
+             CONF_WR_04H : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+                PERR : In    std_logic;\r
+                SERR : In    std_logic;\r
+             CONF_DATA_04H : Out   std_logic_vector (31 downto 0) );\r
+   end component;\r
+\r
+begin\r
+\r
+   CONF_DATA_04H <= CONF_DATA_04H_DUMMY;\r
+   CONF_DATA_10H <= CONF_DATA_10H_DUMMY;\r
+\r
+   I10 : CONFIG_MUX_0\r
+      Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0),\r
+                 CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0),\r
+                 CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0),\r
+                 CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0),\r
+                 CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0),\r
+                 READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0),\r
+                 CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0) );\r
+   I9 : CONFIG_RD_0\r
+      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
+                 CF_RD_COM=>CF_RD_COM,\r
+                 READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) );\r
+   I8 : CONFIG_WR_0\r
+      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
+                 CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,\r
+                 TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,\r
+                 CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );\r
+   I6 : CONFIG_3CH\r
+      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
+                 CONF_WR_3CH=>CONF_WR_3CH, PCI_CLOCK=>PCI_CLOCK,\r
+                 PCI_RSTn=>PCI_RSTn,\r
+                 CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0) );\r
+   I5 : CONFIG_10H\r
+      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
+                 CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK,\r
+                 PCI_RSTn=>PCI_RSTn,\r
+                 CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) );\r
+   I4 : CONFIG_08H\r
+      Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0),\r
+                 CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) );\r
+   I3 : CONFIG_00H\r
+      Port Map ( VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
+                 CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0) );\r
+   I2 : CONFIG_04H\r
+      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
+                 CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK,\r
+                 PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR,\r
+                 CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) );\r
+\r
+end SCHEMATIC;\r
diff --git a/dhwk/source/config_wr_0.vhd b/dhwk/source/config_wr_0.vhd
new file mode 100644 (file)
index 0000000..4156415
--- /dev/null
@@ -0,0 +1,131 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: CONFIG_WR_0.VHD\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity CONFIG_WR_0 is\r
+    port\r
+       (\r
+       ADDR_REG                        :in             std_logic_vector(31 downto 0);\r
+       CF_WR_COM                       :in             std_logic;\r
+       IRDY_REGn                       :in             std_logic;\r
+       TRDYn                                   :in             std_logic;\r
+       CONF_WR_04H             :out    std_logic; \r
+       CONF_WR_10H             :out    std_logic; \r
+       CONF_WR_3CH             :out    std_logic\r
+--CONF_WR_40H          :out    std_logic \r
+    );\r
+end entity CONFIG_WR_0;\r
+\r
+architecture CONFIG_WR_0_DESIGN of CONFIG_WR_0 is\r
+\r
+--\r
+--\r
+--\r
+--\r
+--\r
+--                            PCI Configuration Space Header\r
+--\r
+--       \                        Bit\r
+--                       \\r
+--Address      |31                                     24|23                             16|15                    8|7                           0|      \r
+-----------------------------------------------------------------\r
+--00                   |Device ID                                                                      |Vendor ID                                                      |                                       \r
+--04                   |Status                                                                                 |Command                                                                |\r
+--08                   |Class Code                                                                     |Revision ID                                            |\r
+--0C                   |BIST                           |Header Type            |Latency T.     |Cache L.S.     |\r
+--10-24                |Base Address Register                                                                                                                  |\r
+--28                   |Cardbus CIS Pointer                                                                                                                            |\r
+--2C                   |Subsystem ID                                                           |Subsystem Vendor ID            |\r
+--30                   |Expansion ROM Base Address                                                                                                     |\r
+--34                   |Reserved                                                                                                                                                                               |\r
+--38                   |Reserved                                                                                                                                                                               |\r
+--3C                   |Max_Lat                |Min_Gnt                                |Int_Pin                |Int_Line               |\r
+--40-FF                |                                                                                                                                                                                                               |\r
+-----------------------------------------------------------------\r
+\r
+\r
+--PCI Bus Commands \r
+--C/BE[3..0] Command Type\r
+--------------------------------------\r
+--     0000            Interrupt Acknowledge\r
+--     0001            Special Cycle\r
+--     0010            I/O Read\r
+--     0011            I/O Write\r
+--     0100            Reserved\r
+--     0101            Reserved\r
+--     0110            Memory Read\r
+--     0111            Memory Write\r
+--\r
+--     1000            Reserved\r
+--     1001            Reserved\r
+--     1010            Configuration Read\r
+--     1011            Configuration Write\r
+--     1100            Memory Read Multiple \r
+--     1101            Dual Address Cycle\r
+--     1110            Memory Read Line\r
+--     1111            Memory Write and Invalidate\r
+\r
+\r
+--PCI Byte Enable \r
+--C/BE[3..0] gueltige Datenbits \r
+-------------------------------\r
+--     0000            AD 31..0\r
+--     1000            AD 23..0\r
+--     1100            AD 15..0\r
+--     1110            AD  7..0\r
+\r
+       constant        CMD_INT_ACK                     :std_logic_vector(3 downto 0) := "0000";\r
+       constant        CMD_SP_CYC                      :std_logic_vector(3 downto 0) := "0001";\r
+       constant        CMD_IO_READ                     :std_logic_vector(3 downto 0) := "0010";\r
+       constant        CMD_IO_WRITE            :std_logic_vector(3 downto 0) := "0011";\r
+       constant        CMD_RES_4                               :std_logic_vector(3 downto 0) := "0100";\r
+       constant        CMD_RES_5                               :std_logic_vector(3 downto 0) := "0101";\r
+       constant        CMD_MEM_READ            :std_logic_vector(3 downto 0) := "0110";\r
+       constant        CMD_MEM_WRITE           :std_logic_vector(3 downto 0) := "0111";\r
+       constant        CMD_RES_8                               :std_logic_vector(3 downto 0) := "1000";\r
+       constant        CMD_RES_9                               :std_logic_vector(3 downto 0) := "1001";\r
+       constant        CMD_CONF_READ           :std_logic_vector(3 downto 0) := "1010";\r
+       constant        CMD_CONF_WRITE  :std_logic_vector(3 downto 0) := "1011";\r
+       constant        CMD_MEM_READ_M  :std_logic_vector(3 downto 0) := "1100";\r
+       constant        CMD_DU_ADR_CYC  :std_logic_vector(3 downto 0) := "1101";\r
+       constant        CMD_MEN_READ_L  :std_logic_vector(3 downto 0) := "1110";\r
+       constant        CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";\r
+\r
+       signal          CONFIG_ADDR                     :std_logic_vector(7 downto 0); \r
+       signal          CONFIG_WRITE            :std_logic_vector(3 downto 0); \r
+\r
+\r
+begin\r
+\r
+--*******************************************************************\r
+--******************* PCI Write Configuration Address ***************\r
+--*******************************************************************\r
+\r
+       CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);\r
+\r
+\r
+       process (CF_WR_COM,IRDY_REGn,TRDYn,CONFIG_ADDR) \r
+       begin\r
+\r
+               if      CF_WR_COM = '1' and     IRDY_REGn = '0' and     TRDYn = '0'     then\r
+\r
+                       if                      CONFIG_ADDR = X"04"     then    CONFIG_WRITE    <= "0001";\r
+                               elsif   CONFIG_ADDR = X"10"     then    CONFIG_WRITE    <= "0010";\r
+                               elsif   CONFIG_ADDR = X"3C"     then    CONFIG_WRITE    <= "0100";\r
+--                     elsif   CONFIG_ADDR = X"40"     then    CONFIG_WRITE    <= "1000";\r
+                               else                                                                                                            CONFIG_WRITE    <= "0000";\r
+                       end if;\r
+               else                                                                                                                            CONFIG_WRITE    <= "0000";\r
+               end if;\r
+       end process;\r
+\r
+       CONF_WR_04H     <=      CONFIG_WRITE(0); \r
+       CONF_WR_10H     <=      CONFIG_WRITE(1);         \r
+       CONF_WR_3CH     <=      CONFIG_WRITE(2);        \r
+--CONF_WR_40H  <=      CONFIG_WRITE(3);        \r
+\r
+end architecture CONFIG_WR_0_DESIGN;\r
diff --git a/dhwk/source/connecting_fsm.vhd b/dhwk/source/connecting_fsm.vhd
new file mode 100644 (file)
index 0000000..ab8f54f
--- /dev/null
@@ -0,0 +1,136 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: CONNECTING_FSM.VHD\r
+\r
+library ieee ;\r
+use ieee.std_logic_1164.all ;\r
+\r
+entity CONNECTING_FSM is\r
+       port\r
+       (\r
+       PCI_CLOCK                               :in             std_logic; \r
+       RESET                                           :in             std_logic; \r
+       PSC_ENABLE                      :in             std_logic;\r
+       SYNC_S_FIFO_EFn :in             std_logic;\r
+       SPC_ENABLE                      :in             std_logic;\r
+       SYNC_R_FIFO_FFn :in             std_logic;\r
+       S_FIFO_Q_OUT            :in             std_logic_vector(7 downto 0);\r
+       S_FIFO_READn            :out    std_logic;\r
+       R_FIFO_WRITEn           :out    std_logic;\r
+       R_FIFO_D_IN                     :out    std_logic_vector(7 downto 0) \r
+       );\r
+end entity CONNECTING_FSM;\r
+\r
+architecture CONNECTING_FSM_DESIGN of CONNECTING_FSM is\r
+\r
+       signal REG                                              :std_logic_vector(7 downto 0);\r
+       signal HELP_0,HELP_1    :std_logic;\r
+       signal SIG_LOAD                         :std_logic;\r
+\r
+\r
+--**********************************************************\r
+--***         CONNECTING FSM CODIERUNG                   ***\r
+--**********************************************************\r
+--\r
+--\r
+--                                                 ---------- HELP_0\r
+--                                                      |--------- HELP_1   \r
+--                                                      ||-------- LOAD   \r
+--                                                        |||------- WRITE   \r
+--                                                                                                                                                                                        ||||------ READ   \r
+--                                                                                                                                                                                              |||||     \r
+       constant        S0      :std_logic_vector(4 downto 0)   :=      "00011";--\r
+       constant        S1      :std_logic_vector(4 downto 0)   :=      "01010";--READ\r
+       constant        S2      :std_logic_vector(4 downto 0) :=        "10010";--READ\r
+       constant        S3      :std_logic_vector(4 downto 0) :=        "11110";--READ,LOAD\r
+       constant        S4      :std_logic_vector(4 downto 0) :=        "11011";--\r
+       constant        S5      :std_logic_vector(4 downto 0) :=        "01001";--WRITE\r
+       constant        S6      :std_logic_vector(4 downto 0) :=        "10001";--WRITE\r
+       constant        S7      :std_logic_vector(4 downto 0) :=        "11001";--WRITE\r
+\r
+       signal STATES   :std_logic_vector(4 downto 0);\r
+\r
+--************************************************************\r
+--***             FSM SPEICHER-AUTOMAT                     ***\r
+--************************************************************\r
+\r
+       attribute       syn_state_machine       :       boolean;\r
+       attribute       syn_state_machine       of      STATES  :       signal  is      false;\r
+\r
+--************************************************************\r
+--***                          REGISTER BESCHREIBUNG                  ***\r
+--************************************************************\r
+\r
+begin\r
+\r
+       process (PCI_CLOCK) \r
+       begin\r
+               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then\r
+                       if                      SIG_LOAD        =       '1'     then    REG     <=      S_FIFO_Q_OUT;\r
+                               elsif   SIG_LOAD        =       '0'     then    REG     <=      REG;   \r
+                       end if;\r
+               end if;\r
+       end process;\r
+\r
+--************************************************************\r
+--***                          FSM BESCHREIBUNG                                 ***\r
+--************************************************************\r
+\r
+       process (PCI_CLOCK)\r
+       begin  \r
+               if      (PCI_CLOCK'event        and     PCI_CLOCK       =       '1')    then\r
+  \r
+                       if      RESET   =       '1'     then    STATES <= S0;\r
+                               else\r
+  \r
+                                       case    STATES is\r
+\r
+                                       when    S0      => \r
+                                               if      PSC_ENABLE                      = '1'   and\r
+                                                               SPC_ENABLE                      =       '1'     and\r
+                                                               SYNC_S_FIFO_EFn =       '1'     then\r
+\r
+                                                                                               STATES  <=      S1;\r
+                                                       else  \r
+                                                                                               STATES  <=      S0;\r
+                                               end if;\r
+\r
+                                       when    S1      =>      STATES  <=      S2;\r
+                                       when    S2      =>      STATES  <=      S3;\r
+                                       when    S3      =>      STATES  <=      S4;\r
+\r
+                                       when    S4      => \r
+                                               if      SYNC_R_FIFO_FFn =       '1'     then\r
+\r
+                                                                                               STATES  <=      S5;\r
+                                               else  \r
+                               STATES  <=      S4;\r
+                                               end if;\r
+\r
+                                       when    S5      =>      STATES  <=      S6;\r
+                                       when    S6      =>      STATES  <=      S7;\r
+                                       when    S7      =>      STATES  <=      S0;\r
+\r
+                                       when others => \r
+\r
+                                                                                               STATES  <=      S0; \r
+\r
+                               end case;               -- STATES    \r
+                       end if;                         -- RESET \r
+               end if;                                 -- PCI_CLOCK   \r
+       end process;                    -- PROCESS\r
+\r
+--************************************************************\r
+--***          ZUWEISUNG       signal/out      <=      STATES             ***\r
+--************************************************************\r
+\r
+       HELP_0                          <=      STATES(4);  \r
+       HELP_1                          <=      STATES(3);\r
+       SIG_LOAD                        <=      STATES(2);\r
+       R_FIFO_WRITEn   <=      STATES(1);\r
+       S_FIFO_READn    <=      STATES(0);\r
+\r
+       R_FIFO_D_IN             <=      REG;\r
+\r
+end architecture CONNECTING_FSM_DESIGN;\r
diff --git a/dhwk/source/fifo_control.vhd b/dhwk/source/fifo_control.vhd
new file mode 100644 (file)
index 0000000..7c9ce96
--- /dev/null
@@ -0,0 +1,172 @@
+-- VHDL model created from schematic fifo_control.sch -- Jan 09 09:34:17 2007\r
+\r
+\r
+\r
+LIBRARY ieee;\r
+\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+\r
+entity FIFO_CONTROL is\r
+      Port ( FIFO_RDn : In    std_logic;\r
+             FLAG_IN_0 : In    std_logic;\r
+             FLAG_IN_4 : In    std_logic;\r
+                HOLD : In    std_logic;\r
+             KONST_1 : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PSC_ENABLE : In    std_logic;\r
+               R_EFn : In    std_logic;\r
+               R_FFn : In    std_logic;\r
+               R_HFn : In    std_logic;\r
+               RESET : In    std_logic;\r
+               S_EFn : In    std_logic;\r
+               S_FFn : In    std_logic;\r
+             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
+               S_HFn : In    std_logic;\r
+             SERIAL_IN : In    std_logic;\r
+             SPC_ENABLE : In    std_logic;\r
+             SPC_RDY_IN : In    std_logic;\r
+             WRITE_XX1_0 : In    std_logic;\r
+             R_ERROR : Out   std_logic;\r
+             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
+             R_FIFO_READn : Out   std_logic;\r
+             R_FIFO_RESETn : Out   std_logic;\r
+             R_FIFO_RETRANSMITn : Out   std_logic;\r
+             R_FIFO_WRITEn : Out   std_logic;\r
+             RESERVE : Out   std_logic;\r
+             S_ERROR : Out   std_logic;\r
+             S_FIFO_READn : Out   std_logic;\r
+             S_FIFO_RESETn : Out   std_logic;\r
+             S_FIFO_RETRANSMITn : Out   std_logic;\r
+             S_FIFO_WRITEn : Out   std_logic;\r
+             SERIAL_OUT : Out   std_logic;\r
+             SPC_RDY_OUT : Out   std_logic;\r
+             SR_ERROR : Out   std_logic;\r
+             SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
+end FIFO_CONTROL;\r
+\r
+architecture SCHEMATIC of FIFO_CONTROL is\r
+\r
+   SIGNAL gnd : std_logic := '0';\r
+   SIGNAL vcc : std_logic := '1';\r
+\r
+   signal XXXR_FIFO_WRITEn : std_logic;\r
+   signal XXXS_FIFO_READn : std_logic;\r
+   signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);\r
+   signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);\r
+\r
+   component SER_PAR_CON\r
+      Port ( PCI_CLOCK : In    std_logic;\r
+               RESET : In    std_logic;\r
+             SERIAL_IN : In    std_logic;\r
+             SPC_ENABLE : In    std_logic;\r
+             SYNC_R_FIFO_FFn : In    std_logic;\r
+             PAR_OUT : Out   std_logic_vector (7 downto 0);\r
+             R_FIFO_WRITEn : Out   std_logic;\r
+             SPC_RDY_OUT : Out   std_logic );\r
+   end component;\r
+\r
+   component PAR_SER_CON\r
+      Port (  PAR_IN : In    std_logic_vector (7 downto 0);\r
+             PCI_CLOCK : In    std_logic;\r
+             PSC_ENABLE : In    std_logic;\r
+               RESET : In    std_logic;\r
+             SPC_RDY_IN : In    std_logic;\r
+             SYNC_S_FIFO_EFn : In    std_logic;\r
+             S_FIFO_READn : Out   std_logic;\r
+             SER_OUT : Out   std_logic );\r
+   end component;\r
+\r
+   component FIFO_IO_CONTROL\r
+      Port ( FIFO_RDn : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+               RESET : In    std_logic;\r
+             SYNC_FLAG_1 : In    std_logic;\r
+             SYNC_FLAG_7 : In    std_logic;\r
+             WRITE_XX1_0 : In    std_logic;\r
+             R_ERROR : Out   std_logic;\r
+             R_FIFO_READn : Out   std_logic;\r
+             R_FIFO_RESETn : Out   std_logic;\r
+             R_FIFO_RETRANSMITn : Out   std_logic;\r
+             S_ERROR : Out   std_logic;\r
+             S_FIFO_RESETn : Out   std_logic;\r
+             S_FIFO_RETRANSMITn : Out   std_logic;\r
+             S_FIFO_WRITEn : Out   std_logic;\r
+             SR_ERROR : Out   std_logic );\r
+   end component;\r
+\r
+   component CONNECTING_FSM\r
+      Port ( PCI_CLOCK : In    std_logic;\r
+             PSC_ENABLE : In    std_logic;\r
+               RESET : In    std_logic;\r
+             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
+             SPC_ENABLE : In    std_logic;\r
+             SYNC_R_FIFO_FFn : In    std_logic;\r
+             SYNC_S_FIFO_EFn : In    std_logic;\r
+             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
+             R_FIFO_WRITEn : Out   std_logic;\r
+             S_FIFO_READn : Out   std_logic );\r
+   end component;\r
+\r
+   component FLAG_BUS\r
+      Port ( FLAG_IN_0 : In    std_logic;\r
+             FLAG_IN_4 : In    std_logic;\r
+                HOLD : In    std_logic;\r
+              KONS_1 : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+               R_EFn : In    std_logic;\r
+               R_FFn : In    std_logic;\r
+               R_HFn : In    std_logic;\r
+               S_EFn : In    std_logic;\r
+               S_FFn : In    std_logic;\r
+               S_HFn : In    std_logic;\r
+             SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
+   end component;\r
+\r
+begin\r
+\r
+   SYNC_FLAG <= SYNC_FLAG_DUMMY;\r
+\r
+   RESERVE <= gnd;\r
+   I23 : SER_PAR_CON\r
+      Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
+                 SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,\r
+                 SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
+                 PAR_OUT(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
+                 R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );\r
+   I22 : PAR_SER_CON\r
+      Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
+                 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,\r
+                 RESET=>RESET, SPC_RDY_IN=>SPC_RDY_IN,\r
+                 SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),\r
+                 S_FIFO_READn=>S_FIFO_READn, SER_OUT=>SERIAL_OUT );\r
+   I21 : FIFO_IO_CONTROL\r
+      Port Map ( FIFO_RDn=>FIFO_RDn, PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
+                 SYNC_FLAG_1=>SYNC_FLAG_DUMMY(1),\r
+                 SYNC_FLAG_7=>SYNC_FLAG_DUMMY(7),\r
+                 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
+                 R_FIFO_READn=>R_FIFO_READn,\r
+                 R_FIFO_RESETn=>R_FIFO_RESETn,\r
+                 R_FIFO_RETRANSMITn=>R_FIFO_RETRANSMITn,\r
+                 S_ERROR=>S_ERROR, S_FIFO_RESETn=>S_FIFO_RESETn,\r
+                 S_FIFO_RETRANSMITn=>S_FIFO_RETRANSMITn,\r
+                 S_FIFO_WRITEn=>S_FIFO_WRITEn, SR_ERROR=>SR_ERROR );\r
+   I20 : CONNECTING_FSM\r
+      Port Map ( PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,\r
+                 RESET=>RESET,\r
+                 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
+                 SPC_ENABLE=>SPC_ENABLE,\r
+                 SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
+                 SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),\r
+                 R_FIFO_D_IN(7 downto 0)=>XXXR_FIFO_D_IN(7 downto 0),\r
+                 R_FIFO_WRITEn=>XXXR_FIFO_WRITEn,\r
+                 S_FIFO_READn=>XXXS_FIFO_READn );\r
+   I19 : FLAG_BUS\r
+      Port Map ( FLAG_IN_0=>FLAG_IN_0, FLAG_IN_4=>FLAG_IN_4, HOLD=>HOLD,\r
+                 KONS_1=>KONST_1, PCI_CLOCK=>PCI_CLOCK, R_EFn=>R_EFn,\r
+                 R_FFn=>R_FFn, R_HFn=>R_HFn, S_EFn=>S_EFn, S_FFn=>S_FFn,\r
+                 S_HFn=>S_HFn,\r
+                 SYNC_FLAG(7 downto 0)=>SYNC_FLAG_DUMMY(7 downto 0) );\r
+\r
+end SCHEMATIC;\r
diff --git a/dhwk/source/fifo_io_control.vhd b/dhwk/source/fifo_io_control.vhd
new file mode 100644 (file)
index 0000000..514f078
--- /dev/null
@@ -0,0 +1,110 @@
+-- $Id: fifo_io_control.vhd,v 1.1 2007-03-10 11:24:03 sithglan Exp $\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+\r
+entity FIFO_IO_CONTROL is\r
+       port\r
+       (\r
+       PCI_CLOCK                               :in     std_logic;\r
+       WRITE_XX1_0                             :in     std_logic; -- PCI Write\r
+       FIFO_RDn                                :in     std_logic; -- FIFO Read (low active)\r
+       RESET                                   :in     std_logic;\r
+       SYNC_FLAG_1                             :in     std_logic; -- Recv FIFO Empty (low active)\r
+       SYNC_FLAG_7                             :in     std_logic; -- Send FIFO Full (low active)\r
+       S_FIFO_RESETn                           :out    std_logic; -- Send FIFO Reset (low active)\r
+       R_FIFO_RESETn                           :out    std_logic; -- Recv FIFO Reset (low active)\r
+       S_FIFO_WRITEn                           :out    std_logic; -- Send FIFO Write (low active)\r
+       R_FIFO_READn                            :out    std_logic; -- Recv FIFO Read (low active)\r
+       S_FIFO_RETRANSMITn                      :out    std_logic; -- Send FIFO Retransmit (low active)\r
+       R_FIFO_RETRANSMITn                      :out    std_logic; -- Recv FIFO Retransmit (low active)\r
+       S_ERROR                                 :out    std_logic; -- Send ERROR\r
+       R_ERROR                                 :out    std_logic; -- Recv ERROR\r
+       SR_ERROR                                :out    std_logic  -- Send / Recv Error\r
+       );      \r
+end entity FIFO_IO_CONTROL;\r
+\r
+architecture FIFO_IO_CONTROL_DESIGN of FIFO_IO_CONTROL is\r
+\r
+signal SIG_S_ERROR     :std_logic; -- Send Error\r
+signal SIG_R_ERROR     :std_logic; -- Recv Error\r
+\r
+begin\r
+\r
+-- FIFO Write\r
+\r
+       process (PCI_CLOCK) \r
+       begin \r
+               if (PCI_CLOCK'event and PCI_CLOCK = '1')  then  \r
+                        if (RESET = '1') then\r
+                                S_FIFO_WRITEn <= '1';\r
+                                SIG_S_ERROR   <= '0';\r
+\r
+                        elsif (WRITE_XX1_0 = '0') then\r
+                                S_FIFO_WRITEn <= '1';\r
+\r
+                        elsif (WRITE_XX1_0 = '1') then\r
+                                if (SYNC_FLAG_7 = '0') then\r
+                                        SIG_S_ERROR <= '1';\r
+\r
+                                elsif (SYNC_FLAG_7 = '1') then\r
+                                        S_FIFO_WRITEn <= '0';\r
+                                        SIG_S_ERROR <= '0';\r
+                                end if;\r
+                                                                                               end if;\r
+               end if;\r
+       end process;    \r
+\r
+       S_ERROR <= SIG_S_ERROR;\r
+               \r
+-- FIFO Read\r
+\r
+       R_FIFO_READn <= FIFO_RDn;       \r
+\r
+-- Receive Error\r
+\r
+process (PCI_CLOCK) \r
+begin \r
+        if (PCI_CLOCK'event and PCI_CLOCK ='1')  then  \r
+                if (RESET = '1') then\r
+                        SIG_R_ERROR <= '0';\r
+\r
+                elsif (FIFO_RDn = '0' and SYNC_FLAG_1 = '0') then\r
+                        SIG_R_ERROR <= '1';\r
+                end if;\r
+        end if;\r
+end process; \r
+\r
+       R_ERROR <=      SIG_R_ERROR;            \r
+\r
+-- Send or Receive Error\r
+\r
+process (PCI_CLOCK) \r
+begin \r
+        if (PCI_CLOCK'event and PCI_CLOCK ='1') then  \r
+                SR_ERROR       <= SIG_S_ERROR or SIG_R_ERROR;\r
+        end if;\r
+end process; \r
+\r
+-- FIFO Reset\r
+\r
+process (PCI_CLOCK) \r
+begin \r
+        if (PCI_CLOCK'event and PCI_CLOCK ='1') then  \r
+                S_FIFO_RESETn <= not RESET;    \r
+                R_FIFO_RESETn <= not RESET;    \r
+        end if;\r
+end process;   \r
+\r
+\r
+-- FIFO Retransmit\r
+\r
+process (PCI_CLOCK) \r
+begin \r
+        if (PCI_CLOCK'event and PCI_CLOCK ='1') then  \r
+                S_FIFO_RETRANSMITn <= '1';     \r
+                R_FIFO_RETRANSMITn <= '1';     \r
+        end if;\r
+end process; \r
+       \r
+end architecture FIFO_IO_CONTROL_DESIGN;\r
diff --git a/dhwk/source/io_mux_reg.vhd b/dhwk/source/io_mux_reg.vhd
new file mode 100644 (file)
index 0000000..38f2356
--- /dev/null
@@ -0,0 +1,104 @@
+-- VHDL model created from schematic io_mux_reg.sch -- Jan 09 09:34:13 2007\r
+\r
+\r
+\r
+LIBRARY ieee;\r
+\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+\r
+entity IO_MUX_REG is\r
+      Port ( CONFIG_DATA : In    std_logic_vector (31 downto 0);\r
+             LOAD_ADDR_REG : In    std_logic;\r
+             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_FRAMEn : In    std_logic;\r
+             PCI_IDSEL : In    std_logic;\r
+             PCI_IRDYn : In    std_logic;\r
+             PCI_PAR : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             READ_SEL : In    std_logic_vector (1 downto 0);\r
+             USER_DATA : In    std_logic_vector (31 downto 0);\r
+              PCI_AD : InOut std_logic_vector (31 downto 0);\r
+              AD_REG : Out   std_logic_vector (31 downto 0);\r
+             ADDR_REG : Out   std_logic_vector (31 downto 0);\r
+             CBE_REGn : Out   std_logic_vector (3 downto 0);\r
+             FRAME_REGn : Out   std_logic;\r
+             IDSEL_REG : Out   std_logic;\r
+             IRDY_REGn : Out   std_logic;\r
+             PAR_REG : Out   std_logic );\r
+end IO_MUX_REG;\r
+\r
+architecture SCHEMATIC of IO_MUX_REG is\r
+\r
+   SIGNAL gnd : std_logic := '0';\r
+   SIGNAL vcc : std_logic := '1';\r
+\r
+   signal  IO_DATA : std_logic_vector (31 downto 0);\r
+   signal AD_REG_DUMMY : std_logic_vector (31 downto 0);\r
+\r
+   component ADDR_REGI\r
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
+             LOAD_ADDR_REG : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             ADDR_REG : Out   std_logic_vector (31 downto 0) );\r
+   end component;\r
+\r
+   component IO_REG\r
+      Port ( IO_DATA : In    std_logic_vector (31 downto 0);\r
+             OE_PCI_AD : In    std_logic;\r
+             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_FRAMEn : In    std_logic;\r
+             PCI_IDSEL : In    std_logic;\r
+             PCI_IRDYn : In    std_logic;\r
+             PCI_PAR : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+              AD_REG : Out   std_logic_vector (31 downto 0);\r
+             CBE_REGn : Out   std_logic_vector (3 downto 0);\r
+             FRAME_REGn : Out   std_logic;\r
+             IDSEL_REG : Out   std_logic;\r
+             IRDY_REGn : Out   std_logic;\r
+             PAR_REG : Out   std_logic;\r
+              PCI_AD : Out   std_logic_vector (31 downto 0) );\r
+   end component;\r
+\r
+   component IO_MUX\r
+      Port ( CONFIG_DATA : In    std_logic_vector (31 downto 0);\r
+              PCI_AD : In    std_logic_vector (31 downto 0);\r
+             READ_SEL : In    std_logic_vector (1 downto 0);\r
+             USER_DATA : In    std_logic_vector (31 downto 0);\r
+             IO_DATA : Out   std_logic_vector (31 downto 0) );\r
+   end component;\r
+\r
+begin\r
+\r
+   AD_REG <= AD_REG_DUMMY;\r
+\r
+   I5 : ADDR_REGI\r
+      Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
+                 LOAD_ADDR_REG=>LOAD_ADDR_REG, PCI_CLOCK=>PCI_CLOCK,\r
+                 PCI_RSTn=>PCI_RSTn,\r
+                 ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0) );\r
+   I1 : IO_REG\r
+      Port Map ( IO_DATA(31 downto 0)=>IO_DATA(31 downto 0),\r
+                 OE_PCI_AD=>READ_SEL(1),\r
+                 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
+                 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
+                 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
+                 PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn,\r
+                 AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
+                 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,\r
+                 IRDY_REGn=>IRDY_REGn, PAR_REG=>PAR_REG,\r
+                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0) );\r
+   I2 : IO_MUX\r
+      Port Map ( CONFIG_DATA(31 downto 0)=>CONFIG_DATA(31 downto 0),\r
+                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
+                 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
+                 USER_DATA(31 downto 0)=>USER_DATA(31 downto 0),\r
+                 IO_DATA(31 downto 0)=>IO_DATA(31 downto 0) );\r
+\r
+end SCHEMATIC;\r
diff --git a/dhwk/source/parity.vhd b/dhwk/source/parity.vhd
new file mode 100644 (file)
index 0000000..b0dce43
--- /dev/null
@@ -0,0 +1,106 @@
+-- VHDL model created from schematic parity.sch -- Jan 09 09:34:12 2007\r
+\r
+--LIBRARY vanmacro;\r
+--USE vanmacro.components.ALL;\r
+LIBRARY ieee;\r
+--LIBRARY generics;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+--USE generics.components.ALL;\r
+\r
+entity PARITY is\r
+      Port ( OE_PCI_PAR : In    std_logic;\r
+             OE_PCI_PERR : In    std_logic;\r
+             PA_ER_RE : In    std_logic;\r
+              PAR_IN : In    std_logic_vector (35 downto 0);\r
+             PAR_REG : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             PERR_CHECK : In    std_logic;\r
+             SERR_CHECK : In    std_logic;\r
+             SERR_ENA : In    std_logic;\r
+             PCI_PAR : InOut std_logic;\r
+             PCI_PERRn : Out   std_logic;\r
+             PCI_SERRn : Out   std_logic;\r
+                PERR : Out   std_logic;\r
+                SERR : Out   std_logic );\r
+end PARITY;\r
+\r
+architecture SCHEMATIC of PARITY is\r
+\r
+   SIGNAL gnd : std_logic := '0';\r
+   SIGNAL vcc : std_logic := '1';\r
+\r
+   signal  PAR_OUT : std_logic_vector (10 downto 0);\r
+\r
+   component PARITY_OUT\r
+      Port ( OE_PCI_PAR : In    std_logic;\r
+             OE_PCI_PERR : In    std_logic;\r
+             PA_ER_RE : In    std_logic;\r
+              PAR_IN : In    std_logic_vector (2 downto 0);\r
+             PAR_REG : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_PAR_IN : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             PERR_CHECK : In    std_logic;\r
+             SERR_CHECK : In    std_logic;\r
+             SERR_ENA : In    std_logic;\r
+             PCI_PAR : Out   std_logic;\r
+             PCI_PERRn : Out   std_logic;\r
+             PCI_SERRn : Out   std_logic;\r
+                PERR : Out   std_logic;\r
+                SERR : Out   std_logic );\r
+   end component;\r
+\r
+   component PARITY_4\r
+      Port (  PAR_IN : In    std_logic_vector (3 downto 0);\r
+             PAR_OUT : Out   std_logic );\r
+   end component;\r
+\r
+begin\r
+\r
+   I12 : PARITY_OUT\r
+      Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,\r
+                 PA_ER_RE=>PA_ER_RE,\r
+                 PAR_IN(2 downto 0)=>PAR_OUT(10 downto 8),\r
+                 PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,\r
+                 PCI_PAR_IN=>PCI_PAR, PCI_RSTn=>PCI_RSTn,\r
+                 PERR_CHECK=>PERR_CHECK, SERR_CHECK=>SERR_CHECK,\r
+                 SERR_ENA=>SERR_ENA, PCI_PAR=>PCI_PAR,\r
+                 PCI_PERRn=>PCI_PERRn, PCI_SERRn=>PCI_SERRn, PERR=>PERR,\r
+                 SERR=>SERR );\r
+   I9 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(35 downto 32),\r
+                 PAR_OUT=>PAR_OUT(8) );\r
+   I11 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(7 downto 4),\r
+                 PAR_OUT=>PAR_OUT(10) );\r
+   I8 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(31 downto 28),\r
+                 PAR_OUT=>PAR_OUT(7) );\r
+   I7 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(27 downto 24),\r
+                 PAR_OUT=>PAR_OUT(6) );\r
+   I6 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(23 downto 20),\r
+                 PAR_OUT=>PAR_OUT(5) );\r
+   I5 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(19 downto 16),\r
+                 PAR_OUT=>PAR_OUT(4) );\r
+   I4 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(15 downto 12),\r
+                 PAR_OUT=>PAR_OUT(3) );\r
+   I3 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(11 downto 8),\r
+                 PAR_OUT=>PAR_OUT(2) );\r
+   I2 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(7 downto 4),\r
+                 PAR_OUT=>PAR_OUT(1) );\r
+   I1 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_IN(3 downto 0),\r
+                 PAR_OUT=>PAR_OUT(0) );\r
+   I10 : PARITY_4\r
+      Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(3 downto 0),\r
+                 PAR_OUT=>PAR_OUT(9) );\r
+\r
+end SCHEMATIC;\r
diff --git a/dhwk/source/parity_out.vhd b/dhwk/source/parity_out.vhd
new file mode 100644 (file)
index 0000000..285764d
--- /dev/null
@@ -0,0 +1,66 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: PARITY_OUT.VHD\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+\r
+entity PARITY_OUT is\r
+       port(\r
+               PCI_CLOCK               :in             std_logic;\r
+               PCI_RSTn                :in             std_logic;\r
+               PAR_IN                  :in             std_logic_vector ( 2 downto 0); \r
+               PAR_REG                 :in             std_logic;\r
+               SERR_CHECK      :in             std_logic;      \r
+               PERR_CHECK      :in             std_logic;\r
+               OE_PCI_PAR      :in             std_logic;\r
+               OE_PCI_PERR     :in             std_logic;\r
+               PA_ER_RE                :in             std_logic;\r
+               SERR_ENA                :in             std_logic;\r
+               PCI_PAR_IN      :in             std_logic;\r
+               PERR                            :out    std_logic;\r
+               SERR                            :out    std_logic;\r
+               PCI_PERRn               :out    std_logic;      --      s/t/s\r
+               PCI_SERRn               :out    std_logic;      --      o/d\r
+               PCI_PAR                 :out    std_logic               --      t/s\r
+               );\r
+end entity PARITY_OUT; \r
+\r
+architecture PARITY_OUT_DESIGN of PARITY_OUT is\r
+\r
+       signal PAR                      :std_logic;\r
+       signal PAR_FF           :std_logic;\r
+       signal SERR_FF  :std_logic;\r
+       signal PERR_FF  :std_logic;\r
+  \r
+begin\r
+\r
+       PAR             <= ( PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) ); \r
+\r
+       process (PCI_CLOCK, PCI_RSTn) \r
+       begin\r
+               if      PCI_RSTn = '0'  then    PAR_FF  <= '0';\r
+                                                                                                                       PERR_FF <= '0';\r
+                                                                                                                       SERR_FF <= '0'; \r
+\r
+               elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
+\r
+                       PAR_FF  <=      PAR;\r
+                       SERR_FF <=      ((PCI_PAR_IN xor PAR) and SERR_CHECK) and PA_ER_RE and SERR_ENA and (not SERR_FF);   \r
+                       PERR_FF <=      ((PCI_PAR_IN xor PAR) and PERR_CHECK) and (not PERR_FF);  \r
+\r
+               end if;\r
+       end process; \r
+\r
+       SERR                    <=  SERR_FF;\r
+       PERR                    <=  PERR_FF;\r
+\r
+       PCI_PAR         <= PAR_FF                               when    OE_PCI_PAR      = '1' else 'Z' ; \r
+       PCI_SERRn       <= '0'                                  when    SERR_FF                 = '1' else 'Z' ;\r
+       PCI_PERRn       <= not PERR_FF  when    OE_PCI_PERR     = '1' and PA_ER_RE = '1' else 'Z' ;\r
+\r
+end architecture PARITY_OUT_DESIGN;\r
+\r
+\r
+\r
diff --git a/dhwk/source/pci_interface.vhd b/dhwk/source/pci_interface.vhd
new file mode 100644 (file)
index 0000000..2580750
--- /dev/null
@@ -0,0 +1,227 @@
+-- VHDL model created from schematic pci_interface.sch -- Jan 09 09:34:13 2007\r
+\r
+\r
+\r
+LIBRARY ieee;\r
+\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+\r
+entity PCI_INTERFACE is\r
+      Port ( PCI_CBEn : In    std_logic_vector (3 downto 0);\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_FRAMEn : In    std_logic;\r
+             PCI_IDSEL : In    std_logic;\r
+             PCI_IRDYn : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             READ_FIFO : In    std_logic;\r
+             REVISON_ID : In    std_logic_vector (7 downto 0);\r
+             USER_DATA_OUT : In    std_logic_vector (31 downto 0);\r
+             VENDOR_ID : In    std_logic_vector (15 downto 0);\r
+              PCI_AD : InOut std_logic_vector (31 downto 0);\r
+             PCI_PAR : InOut std_logic;\r
+              AD_REG : Out   std_logic_vector (31 downto 0);\r
+             ADDR_REG : Out   std_logic_vector (31 downto 0);\r
+             CBE_REGn : Out   std_logic_vector (3 downto 0);\r
+             DEVSELn : Out   std_logic;\r
+             FIFO_RDn : Out   std_logic;\r
+             IO_WR_COM : Out   std_logic;\r
+             IRDY_REGn : Out   std_logic;\r
+             PCI_DEVSELn : Out   std_logic;\r
+             PCI_PERRn : Out   std_logic;\r
+             PCI_SERRn : Out   std_logic;\r
+             PCI_STOPn : Out   std_logic;\r
+             PCI_TRDYn : Out   std_logic;\r
+             READ_SEL : Out   std_logic_vector (1 downto 0);\r
+               TRDYn : Out   std_logic );\r
+end PCI_INTERFACE;\r
+\r
+architecture SCHEMATIC of PCI_INTERFACE is\r
+\r
+   SIGNAL gnd : std_logic := '0';\r
+   SIGNAL vcc : std_logic := '1';\r
+\r
+   signal IRDY_REGn_DUMMY : std_logic;\r
+   signal  PAR_REG : std_logic;\r
+   signal     PERR : std_logic;\r
+   signal     SERR : std_logic;\r
+   signal CF_RD_COM : std_logic;\r
+   signal CF_WR_COM : std_logic;\r
+   signal      LAR : std_logic;\r
+   signal  MY_ADDR : std_logic;\r
+   signal SERR_CHECK : std_logic;\r
+   signal IDSEL_REG : std_logic;\r
+   signal FRAME_REGn : std_logic;\r
+   signal PERR_CHECK : std_logic;\r
+   signal OE_PCI_PAR : std_logic;\r
+   signal OE_PCI_PERR : std_logic;\r
+   signal TRDYn_DUMMY : std_logic;\r
+   signal CONF_DATA_10H : std_logic_vector (31 downto 0);\r
+   signal CONF_DATA_04H : std_logic_vector (31 downto 0);\r
+   signal CONF_DATA : std_logic_vector (31 downto 0);\r
+   signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);\r
+   signal CBE_REGn_DUMMY : std_logic_vector (3 downto 0);\r
+   signal AD_REG_DUMMY : std_logic_vector (31 downto 0);\r
+   signal ADDR_REG_DUMMY : std_logic_vector (31 downto 0);\r
+\r
+   component STEUERUNG\r
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
+             CBE_REGn : In    std_logic_vector (3 downto 0);\r
+             FRAME_REGn : In    std_logic;\r
+             IDSEL_REG : In    std_logic;\r
+             IO_SPACE : In    std_logic;\r
+             MY_ADDR : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             READ_FIFO : In    std_logic;\r
+             CF_RD_COM : Out   std_logic;\r
+             CF_WR_COM : Out   std_logic;\r
+             DEVSELn : Out   std_logic;\r
+             FIFO_RDn : Out   std_logic;\r
+             IO_RD_COM : Out   std_logic;\r
+             IO_WR_COM : Out   std_logic;\r
+                 LAR : Out   std_logic;\r
+             OE_PCI_PAR : Out   std_logic;\r
+             OE_PCI_PERR : Out   std_logic;\r
+             PCI_DEVSELn : Out   std_logic;\r
+             PCI_STOPn : Out   std_logic;\r
+             PCI_TRDYn : Out   std_logic;\r
+             PERR_CHECK : Out   std_logic;\r
+                READ : Out   std_logic;\r
+             SERR_CHECK : Out   std_logic;\r
+               TRDYn : Out   std_logic );\r
+   end component;\r
+\r
+   component PARITY\r
+      Port ( OE_PCI_PAR : In    std_logic;\r
+             OE_PCI_PERR : In    std_logic;\r
+             PA_ER_RE : In    std_logic;\r
+              PAR_IN : In    std_logic_vector (35 downto 0);\r
+             PAR_REG : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             PERR_CHECK : In    std_logic;\r
+             SERR_CHECK : In    std_logic;\r
+             SERR_ENA : In    std_logic;\r
+             PCI_PAR : InOut std_logic;\r
+             PCI_PERRn : Out   std_logic;\r
+             PCI_SERRn : Out   std_logic;\r
+                PERR : Out   std_logic;\r
+                SERR : Out   std_logic );\r
+   end component;\r
+\r
+   component VERGLEICH\r
+      Port (    IN_A : In    std_logic_vector (31 downto 0);\r
+                IN_B : In    std_logic_vector (31 downto 0);\r
+             GLEICH_OUT : Out   std_logic );\r
+   end component;\r
+\r
+   component IO_MUX_REG\r
+      Port ( CONFIG_DATA : In    std_logic_vector (31 downto 0);\r
+             LOAD_ADDR_REG : In    std_logic;\r
+             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_FRAMEn : In    std_logic;\r
+             PCI_IDSEL : In    std_logic;\r
+             PCI_IRDYn : In    std_logic;\r
+             PCI_PAR : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             READ_SEL : In    std_logic_vector (1 downto 0);\r
+             USER_DATA : In    std_logic_vector (31 downto 0);\r
+              PCI_AD : InOut std_logic_vector (31 downto 0);\r
+              AD_REG : Out   std_logic_vector (31 downto 0);\r
+             ADDR_REG : Out   std_logic_vector (31 downto 0);\r
+             CBE_REGn : Out   std_logic_vector (3 downto 0);\r
+             FRAME_REGn : Out   std_logic;\r
+             IDSEL_REG : Out   std_logic;\r
+             IRDY_REGn : Out   std_logic;\r
+             PAR_REG : Out   std_logic );\r
+   end component;\r
+\r
+   component CONFIG_SPACE_HEADER\r
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
+             ADDR_REG : In    std_logic_vector (31 downto 0);\r
+             CBE_REGn : In    std_logic_vector (3 downto 0);\r
+             CF_RD_COM : In    std_logic;\r
+             CF_WR_COM : In    std_logic;\r
+             IRDY_REGn : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+                PERR : In    std_logic;\r
+             REVISION_ID : In    std_logic_vector (7 downto 0);\r
+                SERR : In    std_logic;\r
+               TRDYn : In    std_logic;\r
+             VENDOR_ID : In    std_logic_vector (15 downto 0);\r
+             CONF_DATA : Out   std_logic_vector (31 downto 0);\r
+             CONF_DATA_04H : Out   std_logic_vector (31 downto 0);\r
+             CONF_DATA_10H : Out   std_logic_vector (31 downto 0) );\r
+   end component;\r
+\r
+begin\r
+\r
+   ADDR_REG <= ADDR_REG_DUMMY;\r
+   AD_REG <= AD_REG_DUMMY;\r
+   CBE_REGn <= CBE_REGn_DUMMY;\r
+   READ_SEL <= READ_SEL_DUMMY;\r
+   TRDYn <= TRDYn_DUMMY;\r
+   IRDY_REGn <= IRDY_REGn_DUMMY;\r
+\r
+   I7 : STEUERUNG\r
+      Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
+                 CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),\r
+                 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,\r
+                 IO_SPACE=>CONF_DATA_04H(0), MY_ADDR=>MY_ADDR,\r
+                 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
+                 READ_FIFO=>READ_FIFO, CF_RD_COM=>CF_RD_COM,\r
+                 CF_WR_COM=>CF_WR_COM, DEVSELn=>DEVSELn,\r
+                 FIFO_RDn=>FIFO_RDn, IO_RD_COM=>READ_SEL_DUMMY(0),\r
+                 IO_WR_COM=>IO_WR_COM, LAR=>LAR, OE_PCI_PAR=>OE_PCI_PAR,\r
+                 OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,\r
+                 PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,\r
+                 PERR_CHECK=>PERR_CHECK, READ=>READ_SEL_DUMMY(1),\r
+                 SERR_CHECK=>SERR_CHECK, TRDYn=>TRDYn_DUMMY );\r
+   I5 : PARITY\r
+      Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,\r
+                 PA_ER_RE=>CONF_DATA_04H(6),\r
+                 PAR_IN(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
+                 PAR_IN(35 downto 32)=>CBE_REGn_DUMMY(3 downto 0),\r
+                 PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,\r
+                 PCI_RSTn=>PCI_RSTn, PERR_CHECK=>PERR_CHECK,\r
+                 SERR_CHECK=>SERR_CHECK, SERR_ENA=>CONF_DATA_04H(8),\r
+                 PCI_PAR=>PCI_PAR, PCI_PERRn=>PCI_PERRn,\r
+                 PCI_SERRn=>PCI_SERRn, PERR=>PERR, SERR=>SERR );\r
+   I4 : VERGLEICH\r
+      Port Map ( IN_A(31 downto 0)=>CONF_DATA_10H(31 downto 0),\r
+                 IN_B(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
+                 GLEICH_OUT=>MY_ADDR );\r
+   I2 : IO_MUX_REG\r
+      Port Map ( CONFIG_DATA(31 downto 0)=>CONF_DATA(31 downto 0),\r
+                 LOAD_ADDR_REG=>LAR,\r
+                 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
+                 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
+                 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
+                 PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn,\r
+                 READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),\r
+                 USER_DATA(31 downto 0)=>USER_DATA_OUT(31 downto 0),\r
+                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
+                 AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
+                 ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),\r
+                 CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),\r
+                 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,\r
+                 IRDY_REGn=>IRDY_REGn_DUMMY, PAR_REG=>PAR_REG );\r
+   I1 : CONFIG_SPACE_HEADER\r
+      Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
+                 ADDR_REG(31 downto 0)=>ADDR_REG_DUMMY(31 downto 0),\r
+                 CBE_REGn(3 downto 0)=>CBE_REGn_DUMMY(3 downto 0),\r
+                 CF_RD_COM=>CF_RD_COM, CF_WR_COM=>CF_WR_COM,\r
+                 IRDY_REGn=>IRDY_REGn_DUMMY, PCI_CLOCK=>PCI_CLOCK,\r
+                 PCI_RSTn=>PCI_RSTn, PERR=>PERR,\r
+                 REVISION_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
+                 SERR=>SERR, TRDYn=>TRDYn_DUMMY,\r
+                 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
+                 CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0),\r
+                 CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H(31 downto 0),\r
+                 CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H(31 downto 0) );\r
+\r
+end SCHEMATIC;\r
diff --git a/dhwk/source/pci_top.vhd b/dhwk/source/pci_top.vhd
new file mode 100644 (file)
index 0000000..64c94d6
--- /dev/null
@@ -0,0 +1,165 @@
+-- VHDL model created from schematic pci_top.sch -- Jan 09 09:34:14 2007\r
+\r
+\r
+\r
+LIBRARY ieee;\r
+\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+\r
+entity PCI_TOP is\r
+      Port (    FLAG : In    std_logic_vector (7 downto 0);\r
+             INT_REG : In    std_logic_vector (7 downto 0);\r
+             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_FRAMEn : In    std_logic;\r
+             PCI_IDSEL : In    std_logic;\r
+             PCI_IRDYn : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             R_FIFO_Q : In    std_logic_vector (7 downto 0);\r
+             REVISON_ID : In    std_logic_vector (7 downto 0);\r
+             VENDOR_ID : In    std_logic_vector (15 downto 0);\r
+              PCI_AD : InOut std_logic_vector (31 downto 0);\r
+             PCI_PAR : InOut std_logic;\r
+              AD_REG : Out   std_logic_vector (31 downto 0);\r
+             DEVSELn : Out   std_logic;\r
+             FIFO_RDn : Out   std_logic;\r
+             PCI_DEVSELn : Out   std_logic;\r
+             PCI_PERRn : Out   std_logic;\r
+             PCI_SERRn : Out   std_logic;\r
+             PCI_STOPn : Out   std_logic;\r
+             PCI_TRDYn : Out   std_logic;\r
+             READ_SEL : Out   std_logic_vector (1 downto 0);\r
+             READ_XX1_0 : Out   std_logic;\r
+             READ_XX3_2 : Out   std_logic;\r
+             READ_XX5_4 : Out   std_logic;\r
+             READ_XX7_6 : Out   std_logic;\r
+             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);\r
+             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);\r
+             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0);\r
+               TRDYn : Out   std_logic;\r
+             WRITE_XX1_0 : Out   std_logic;\r
+             WRITE_XX3_2 : Out   std_logic;\r
+             WRITE_XX5_4 : Out   std_logic;\r
+             WRITE_XX7_6 : Out   std_logic );\r
+end PCI_TOP;\r
+\r
+architecture SCHEMATIC of PCI_TOP is\r
+\r
+   SIGNAL gnd : std_logic := '0';\r
+   SIGNAL vcc : std_logic := '1';\r
+\r
+   signal IRDY_REGn : std_logic;\r
+   signal IO_WR_COM : std_logic;\r
+   signal TRDYn_DUMMY : std_logic;\r
+   signal READ_XX3_2_DUMMY : std_logic;\r
+   signal USER_DATA_OUT : std_logic_vector (31 downto 0);\r
+   signal CBE_REGn : std_logic_vector (3 downto 0);\r
+   signal AD_REG_DUMMY : std_logic_vector (31 downto 0);\r
+   signal ADDR_REG : std_logic_vector (31 downto 0);\r
+   signal READ_SEL_DUMMY : std_logic_vector (1 downto 0);\r
+\r
+   component USER_IO\r
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
+             ADDR_REG : In    std_logic_vector (31 downto 0);\r
+             CBE_REGn : In    std_logic_vector (3 downto 0);\r
+                FLAG : In    std_logic_vector (7 downto 0);\r
+             INT_REG : In    std_logic_vector (7 downto 0);\r
+             IO_WR_COM : In    std_logic;\r
+             IRDY_REGn : In    std_logic;\r
+             PCI_CLK : In    std_logic;\r
+             R_FIFO_Q : In    std_logic_vector (7 downto 0);\r
+             READ_SEL : In    std_logic_vector (1 downto 0);\r
+               TRDYn : In    std_logic;\r
+             READ_XX1_0 : Out   std_logic;\r
+             READ_XX3_2 : Out   std_logic;\r
+             READ_XX5_4 : Out   std_logic;\r
+             READ_XX7_6 : Out   std_logic;\r
+             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);\r
+             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);\r
+             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0);\r
+             USER_DATA_OUT : Out   std_logic_vector (31 downto 0);\r
+             WRITE_XX1_0 : Out   std_logic;\r
+             WRITE_XX3_2 : Out   std_logic;\r
+             WRITE_XX5_4 : Out   std_logic;\r
+             WRITE_XX7_6 : Out   std_logic );\r
+   end component;\r
+\r
+   component PCI_INTERFACE\r
+      Port ( PCI_CBEn : In    std_logic_vector (3 downto 0);\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_FRAMEn : In    std_logic;\r
+             PCI_IDSEL : In    std_logic;\r
+             PCI_IRDYn : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             READ_FIFO : In    std_logic;\r
+             REVISON_ID : In    std_logic_vector (7 downto 0);\r
+             USER_DATA_OUT : In    std_logic_vector (31 downto 0);\r
+             VENDOR_ID : In    std_logic_vector (15 downto 0);\r
+              PCI_AD : InOut std_logic_vector (31 downto 0);\r
+             PCI_PAR : InOut std_logic;\r
+              AD_REG : Out   std_logic_vector (31 downto 0);\r
+             ADDR_REG : Out   std_logic_vector (31 downto 0);\r
+             CBE_REGn : Out   std_logic_vector (3 downto 0);\r
+             DEVSELn : Out   std_logic;\r
+             FIFO_RDn : Out   std_logic;\r
+             IO_WR_COM : Out   std_logic;\r
+             IRDY_REGn : Out   std_logic;\r
+             PCI_DEVSELn : Out   std_logic;\r
+             PCI_PERRn : Out   std_logic;\r
+             PCI_SERRn : Out   std_logic;\r
+             PCI_STOPn : Out   std_logic;\r
+             PCI_TRDYn : Out   std_logic;\r
+             READ_SEL : Out   std_logic_vector (1 downto 0);\r
+               TRDYn : Out   std_logic );\r
+   end component;\r
+\r
+begin\r
+\r
+   READ_SEL <= READ_SEL_DUMMY;\r
+   AD_REG <= AD_REG_DUMMY;\r
+   READ_XX3_2 <= READ_XX3_2_DUMMY;\r
+   TRDYn <= TRDYn_DUMMY;\r
+\r
+   I19 : USER_IO\r
+      Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
+                 ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
+                 FLAG(7 downto 0)=>FLAG(7 downto 0),\r
+                 INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
+                 IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,\r
+                 PCI_CLK=>PCI_CLOCK,\r
+                 R_FIFO_Q(7 downto 0)=>R_FIFO_Q(7 downto 0),\r
+                 READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),\r
+                 TRDYn=>TRDYn_DUMMY, READ_XX1_0=>READ_XX1_0,\r
+                 READ_XX3_2=>READ_XX3_2_DUMMY, READ_XX5_4=>READ_XX5_4,\r
+                 READ_XX7_6=>READ_XX7_6,\r
+                 REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0(7 downto 0),\r
+                 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
+                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
+                 USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),\r
+                 WRITE_XX1_0=>WRITE_XX1_0, WRITE_XX3_2=>WRITE_XX3_2,\r
+                 WRITE_XX5_4=>WRITE_XX5_4, WRITE_XX7_6=>WRITE_XX7_6 );\r
+   I10 : PCI_INTERFACE\r
+      Port Map ( PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
+                 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
+                 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
+                 PCI_RSTn=>PCI_RSTn, READ_FIFO=>READ_XX3_2_DUMMY,\r
+                 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
+                 USER_DATA_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),\r
+                 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
+                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
+                 PCI_PAR=>PCI_PAR,\r
+                 AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
+                 ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
+                 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,\r
+                 IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,\r
+                 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,\r
+                 PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,\r
+                 PCI_TRDYn=>PCI_TRDYn,\r
+                 READ_SEL(1 downto 0)=>READ_SEL_DUMMY(1 downto 0),\r
+                 TRDYn=>TRDYn_DUMMY );\r
+\r
+end SCHEMATIC;\r
diff --git a/dhwk/source/reg_io.vhd b/dhwk/source/reg_io.vhd
new file mode 100644 (file)
index 0000000..1e33810
--- /dev/null
@@ -0,0 +1,54 @@
+-- VHDL model created from schematic reg_io.sch -- Jan 09 09:34:12 2007\r
+\r
+\r
+\r
+LIBRARY ieee;\r
+\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+\r
+entity REG_IO is\r
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
+             PCI_CLOCK : In    std_logic;\r
+               RESET : In    std_logic;\r
+             WRITE_XX1_0 : In    std_logic;\r
+             WRITE_XX7_6 : In    std_logic;\r
+             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);\r
+             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);\r
+             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0) );\r
+end REG_IO;\r
+\r
+architecture SCHEMATIC of REG_IO is\r
+\r
+   SIGNAL gnd : std_logic := '0';\r
+   SIGNAL vcc : std_logic := '1';\r
+\r
+\r
+   component REG\r
+      Port (   CLOCK : In    std_logic;\r
+              REG_IN : In    std_logic_vector (7 downto 0);\r
+               RESET : In    std_logic;\r
+               WRITE : In    std_logic;\r
+             REG_OUT : Out   std_logic_vector (7 downto 0) );\r
+   end component;\r
+\r
+begin\r
+\r
+   I14 : REG\r
+      Port Map ( CLOCK=>PCI_CLOCK,\r
+                 REG_IN(7 downto 0)=>AD_REG(7 downto 0), RESET=>RESET,\r
+                 WRITE=>WRITE_XX1_0,\r
+                 REG_OUT(7 downto 0)=>REG_OUT_XX0(7 downto 0) );\r
+   I15 : REG\r
+      Port Map ( CLOCK=>PCI_CLOCK,\r
+                 REG_IN(7 downto 0)=>AD_REG(31 downto 24), RESET=>RESET,\r
+                 WRITE=>WRITE_XX7_6,\r
+                 REG_OUT(7 downto 0)=>REG_OUT_XX7(7 downto 0) );\r
+   I16 : REG\r
+      Port Map ( CLOCK=>PCI_CLOCK,\r
+                 REG_IN(7 downto 0)=>AD_REG(23 downto 16), RESET=>RESET,\r
+                 WRITE=>WRITE_XX7_6,\r
+                 REG_OUT(7 downto 0)=>REG_OUT_XX6(7 downto 0) );\r
+\r
+end SCHEMATIC;\r
diff --git a/dhwk/source/steuerung.vhd b/dhwk/source/steuerung.vhd
new file mode 100644 (file)
index 0000000..90922dc
--- /dev/null
@@ -0,0 +1,131 @@
+-- VHDL model created from schematic steuerung.sch -- Jan 09 09:34:14 2007\r
+\r
+-- LIBRARY vanmacro;\r
+-- USE vanmacro.components.ALL;\r
+LIBRARY ieee;\r
+--LIBRARY generics;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+--USE generics.components.ALL;\r
+\r
+entity STEUERUNG is\r
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
+             CBE_REGn : In    std_logic_vector (3 downto 0);\r
+             FRAME_REGn : In    std_logic;\r
+             IDSEL_REG : In    std_logic;\r
+             IO_SPACE : In    std_logic;\r
+             MY_ADDR : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             READ_FIFO : In    std_logic;\r
+             CF_RD_COM : Out   std_logic;\r
+             CF_WR_COM : Out   std_logic;\r
+             DEVSELn : Out   std_logic;\r
+             FIFO_RDn : Out   std_logic;\r
+             IO_RD_COM : Out   std_logic;\r
+             IO_WR_COM : Out   std_logic;\r
+                 LAR : Out   std_logic;\r
+             OE_PCI_PAR : Out   std_logic;\r
+             OE_PCI_PERR : Out   std_logic;\r
+             PCI_DEVSELn : Out   std_logic;\r
+             PCI_STOPn : Out   std_logic;\r
+             PCI_TRDYn : Out   std_logic;\r
+             PERR_CHECK : Out   std_logic;\r
+                READ : Out   std_logic;\r
+             SERR_CHECK : Out   std_logic;\r
+               TRDYn : Out   std_logic );\r
+end STEUERUNG;\r
+\r
+architecture SCHEMATIC of STEUERUNG is\r
+\r
+   SIGNAL gnd : std_logic := '0';\r
+   SIGNAL vcc : std_logic := '1';\r
+\r
+   signal DEVSELn_DUMMY : std_logic;\r
+   signal  IO_READ : std_logic;\r
+   signal IO_WRITE : std_logic;\r
+   signal CONF_READ : std_logic;\r
+   signal CONF_WRITE : std_logic;\r
+\r
+   component CONT_FSM\r
+      Port ( CONF_READ : In    std_logic;\r
+             CONF_WRITE : In    std_logic;\r
+             FIFO_READ : In    std_logic;\r
+             IO_READ : In    std_logic;\r
+             IO_WRITE : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             DEVSELn : Out   std_logic;\r
+             FIFO_RDn : Out   std_logic;\r
+             OE_PCI_PAR : Out   std_logic;\r
+             OE_PCI_PERR : Out   std_logic;\r
+             PCI_DEVSELn : Out   std_logic;\r
+             PCI_STOPn : Out   std_logic;\r
+             PCI_TRDYn : Out   std_logic;\r
+             PERR_CHECK : Out   std_logic;\r
+                READ : Out   std_logic;\r
+               TRDYn : Out   std_logic );\r
+   end component;\r
+\r
+   component COMM_FSM\r
+      Port ( CONF_READ : In    std_logic;\r
+             CONF_WRITE : In    std_logic;\r
+             DEVSELn : In    std_logic;\r
+             IO_READ : In    std_logic;\r
+             IO_WRITE : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             CF_RD_COM : Out   std_logic;\r
+             CF_WR_COM : Out   std_logic;\r
+             IO_RD_COM : Out   std_logic;\r
+             IO_WR_COM : Out   std_logic );\r
+   end component;\r
+\r
+   component COMM_DEC\r
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
+             CBE_REGn : In    std_logic_vector (3 downto 0);\r
+             FRAME_REGn : In    std_logic;\r
+             IDSEL_REG : In    std_logic;\r
+             IO_SPACE : In    std_logic;\r
+             MY_ADDR : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             CONF_READ : Out   std_logic;\r
+             CONF_WRITE : Out   std_logic;\r
+             IO_READ : Out   std_logic;\r
+             IO_WRITE : Out   std_logic;\r
+                 LAR : Out   std_logic;\r
+             SERR_CHECK : Out   std_logic );\r
+   end component;\r
+\r
+begin\r
+\r
+   DEVSELn <= DEVSELn_DUMMY;\r
+\r
+   I1 : CONT_FSM\r
+      Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,\r
+                 FIFO_READ=>READ_FIFO, IO_READ=>IO_READ,\r
+                 IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,\r
+                 PCI_RSTn=>PCI_RSTn, DEVSELn=>DEVSELn_DUMMY,\r
+                 FIFO_RDn=>FIFO_RDn, OE_PCI_PAR=>OE_PCI_PAR,\r
+                 OE_PCI_PERR=>OE_PCI_PERR, PCI_DEVSELn=>PCI_DEVSELn,\r
+                 PCI_STOPn=>PCI_STOPn, PCI_TRDYn=>PCI_TRDYn,\r
+                 PERR_CHECK=>PERR_CHECK, READ=>READ, TRDYn=>TRDYn );\r
+   I2 : COMM_FSM\r
+      Port Map ( CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,\r
+                 DEVSELn=>DEVSELn_DUMMY, IO_READ=>IO_READ,\r
+                 IO_WRITE=>IO_WRITE, PCI_CLOCK=>PCI_CLOCK,\r
+                 PCI_RSTn=>PCI_RSTn, CF_RD_COM=>CF_RD_COM,\r
+                 CF_WR_COM=>CF_WR_COM, IO_RD_COM=>IO_RD_COM,\r
+                 IO_WR_COM=>IO_WR_COM );\r
+   I3 : COMM_DEC\r
+      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
+                 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,\r
+                 IO_SPACE=>IO_SPACE, MY_ADDR=>MY_ADDR,\r
+                 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
+                 CONF_READ=>CONF_READ, CONF_WRITE=>CONF_WRITE,\r
+                 IO_READ=>IO_READ, IO_WRITE=>IO_WRITE, LAR=>LAR,\r
+                 SERR_CHECK=>SERR_CHECK );\r
+\r
+end SCHEMATIC;\r
diff --git a/dhwk/source/synplify.vhd b/dhwk/source/synplify.vhd
new file mode 100644 (file)
index 0000000..904bf0d
--- /dev/null
@@ -0,0 +1,184 @@
+-----------------------------------------------------------------------------\r
+--                                                                         --\r
+-- Copyright (c) 1997 by Synplicity, Inc.  All rights reserved.            --\r
+--                                                                         --\r
+-- This source file may be used and distributed without restriction        --\r
+-- provided that this copyright statement is not removed from the file     --\r
+-- and that any derivative work contains this copyright notice.            --\r
+--                                                                         --\r
+-- Primitive library for post synthesis simulation                         --\r
+-- These models are not intended for efficient synthesis                   --\r
+--                                                                         --\r
+-----------------------------------------------------------------------------\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+entity prim_counter is\r
+    generic (w : integer := 8);\r
+    port (\r
+        q : buffer std_logic_vector(w - 1 downto 0);\r
+        cout : out std_logic;\r
+        d : in std_logic_vector(w - 1 downto 0);\r
+        cin : in std_logic;\r
+        clk : in std_logic;\r
+        rst : in std_logic;\r
+        load : in std_logic;\r
+        en : in std_logic;\r
+        updn : in std_logic\r
+    );\r
+end prim_counter;\r
+\r
+architecture beh of prim_counter is\r
+    signal nextq : std_logic_vector(w - 1 downto 0);\r
+begin\r
+    nxt: process (q, cin, updn)\r
+        variable i : integer;\r
+        variable nextc, c : std_logic;\r
+    begin\r
+        nextc := cin;\r
+        for i in 0 to w - 1 loop\r
+            c := nextc;\r
+            nextq(i) <= c xor (not updn) xor q(i);\r
+            nextc := (c and (not updn)) or \r
+                 (c and q(i)) or\r
+                 ((not updn) and q(i));\r
+        end loop;\r
+        cout <= nextc;\r
+    end process;\r
+\r
+    ff : process (clk, rst)\r
+    begin\r
+        if rst = '1' then\r
+            q <= (others => '0');\r
+        elsif rising_edge(clk) then\r
+            q <= nextq;\r
+        end if;\r
+    end process ff;\r
+end beh;\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+entity prim_dff is\r
+    port (q : out std_logic;\r
+          d : in std_logic;\r
+          clk : in std_logic;\r
+          r : in std_logic := '0';\r
+          s : in std_logic := '0');\r
+end prim_dff;\r
+\r
+architecture beh of prim_dff is\r
+begin\r
+    ff : process (clk, r, s)\r
+    begin\r
+        if r = '1' then\r
+            q <= '0';\r
+        elsif s = '1' then\r
+            q <= '1';\r
+        elsif rising_edge(clk) then\r
+            q <= d;\r
+        end if;\r
+    end process ff;\r
+end beh;\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+entity prim_latch is\r
+    port (q : out std_logic;\r
+          d : in std_logic;\r
+          clk : in std_logic;\r
+          r : in std_logic := '0';\r
+          s : in std_logic := '0');\r
+end prim_latch;\r
+\r
+architecture beh of prim_latch is\r
+begin\r
+    q <= '0' when r = '1' else\r
+         '1' when s = '1' else\r
+         d when clk = '1';\r
+end beh;\r
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.std_logic_unsigned.all;\r
+\r
+entity prim_ramd is\r
+generic (\r
+   data_width : integer := 4;\r
+    addr_width : integer := 5);\r
+port (\r
+    dout : out std_logic_vector(data_width-1 downto 0);\r
+    aout : in std_logic_vector(addr_width-1 downto 0);\r
+    din  : in std_logic_vector(data_width-1 downto 0);\r
+    ain : in std_logic_vector(addr_width-1 downto 0);\r
+    we   : in std_logic;\r
+    clk  : in std_logic);\r
+end prim_ramd;\r
+\r
+architecture beh of prim_ramd is\r
+\r
+constant depth : integer := 2** addr_width;\r
+type mem_type is array (depth-1 downto 0) of std_logic_vector (data_width-1 downto 0);\r
+signal mem: mem_type;\r
+\r
+begin  \r
+\r
+dout <= mem(conv_integer(aout));\r
+\r
+process (clk)\r
+    begin\r
+        if rising_edge(clk) then    \r
+            if (we = '1') then\r
+                mem(conv_integer(ain)) <= din;\r
+            end if;\r
+        end if;\r
+end process;\r
+\r
+end beh ;\r
+\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+package components is\r
+    component prim_counter\r
+        generic (w : integer);\r
+        port (\r
+            q : buffer std_logic_vector(w - 1 downto 0);\r
+            cout : out std_logic;\r
+            d : in std_logic_vector(w - 1 downto 0);\r
+            cin : in std_logic;\r
+            clk : in std_logic;\r
+            rst : in std_logic;\r
+            load : in std_logic;\r
+            en : in std_logic;\r
+            updn : in std_logic\r
+        );\r
+    end component;\r
+    component prim_dff\r
+        port (q : out std_logic;\r
+              d : in std_logic;\r
+              clk : in std_logic;\r
+              r : in std_logic := '0';\r
+              s : in std_logic := '0');\r
+    end component;\r
+    component prim_latch\r
+        port (q : out std_logic;\r
+              d : in std_logic;\r
+              clk : in std_logic;\r
+              r : in std_logic := '0';\r
+              s : in std_logic := '0');\r
+    end component;\r
+\r
+    component prim_ramd is\r
+    generic (\r
+        data_width : integer := 4;\r
+        addr_width : integer := 5);\r
+    port (\r
+        dout : out std_logic_vector(data_width-1 downto 0);\r
+        aout : in std_logic_vector(addr_width-1 downto 0);\r
+        din  : in std_logic_vector(data_width-1 downto 0);\r
+        ain : in std_logic_vector(addr_width-1 downto 0);\r
+        we   : in std_logic;\r
+        clk  : in std_logic);\r
+    end component;\r
+\r
+end components;\r
diff --git a/dhwk/source/top.vhd b/dhwk/source/top.vhd
new file mode 100644 (file)
index 0000000..2dc252a
--- /dev/null
@@ -0,0 +1,270 @@
+-- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007\r
+\r
+\r
+\r
+LIBRARY ieee;\r
+\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+\r
+entity TOP is\r
+      Port ( KONST_1 : In    std_logic;\r
+             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_FRAMEn : In    std_logic;\r
+             PCI_IDSEL : In    std_logic;\r
+             PCI_IRDYn : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+               R_EFn : In    std_logic;\r
+               R_FFn : In    std_logic;\r
+             R_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
+               R_HFn : In    std_logic;\r
+               S_EFn : In    std_logic;\r
+               S_FFn : In    std_logic;\r
+             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
+               S_HFn : In    std_logic;\r
+             SERIAL_IN : In    std_logic;\r
+             SPC_RDY_IN : In    std_logic;\r
+             TAST_RESn : In    std_logic;\r
+             TAST_SETn : In    std_logic;\r
+              PCI_AD : InOut std_logic_vector (31 downto 0);\r
+             PCI_PAR : InOut std_logic;\r
+             PCI_DEVSELn : Out   std_logic;\r
+             PCI_INTAn : Out   std_logic;\r
+             PCI_PERRn : Out   std_logic;\r
+             PCI_SERRn : Out   std_logic;\r
+             PCI_STOPn : Out   std_logic;\r
+             PCI_TRDYn : Out   std_logic;\r
+             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
+             R_FIFO_READn : Out   std_logic;\r
+             R_FIFO_RESETn : Out   std_logic;\r
+             R_FIFO_RTn : Out   std_logic;\r
+             R_FIFO_WRITEn : Out   std_logic;\r
+             S_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
+             S_FIFO_READn : Out   std_logic;\r
+             S_FIFO_RESETn : Out   std_logic;\r
+             S_FIFO_RTn : Out   std_logic;\r
+             S_FIFO_WRITEn : Out   std_logic;\r
+             SERIAL_OUT : Out   std_logic;\r
+             SPC_RDY_OUT : Out   std_logic;\r
+             TB_IDSEL : Out   std_logic;\r
+             TB_nDEVSEL : Out   std_logic;\r
+             TB_nINTA : Out   std_logic );\r
+end TOP;\r
+\r
+architecture SCHEMATIC of TOP is\r
+\r
+   SIGNAL gnd : std_logic := '0';\r
+   SIGNAL vcc : std_logic := '1';\r
+\r
+   signal READ_XX7_6 : std_logic;\r
+   signal  RESERVE : std_logic;\r
+   signal SR_ERROR : std_logic;\r
+   signal  R_ERROR : std_logic;\r
+   signal  S_ERROR : std_logic;\r
+   signal WRITE_XX3_2 : std_logic;\r
+   signal WRITE_XX5_4 : std_logic;\r
+   signal WRITE_XX7_6 : std_logic;\r
+   signal READ_XX1_0 : std_logic;\r
+   signal READ_XX3_2 : std_logic;\r
+   signal    INTAn : std_logic;\r
+   signal    TRDYn : std_logic;\r
+   signal READ_XX5_4 : std_logic;\r
+   signal  DEVSELn : std_logic;\r
+   signal FIFO_RDn : std_logic;\r
+   signal WRITE_XX1_0 : std_logic;\r
+   signal REG_OUT_XX6 : std_logic_vector (7 downto 0);\r
+   signal SYNC_FLAG : std_logic_vector (7 downto 0);\r
+   signal  INT_REG : std_logic_vector (7 downto 0);\r
+   signal REVISON_ID : std_logic_vector (7 downto 0);\r
+   signal VENDOR_ID : std_logic_vector (15 downto 0);\r
+   signal READ_SEL : std_logic_vector (1 downto 0);\r
+   signal   AD_REG : std_logic_vector (31 downto 0);\r
+   signal REG_OUT_XX7 : std_logic_vector (7 downto 0);\r
+\r
+   component MESS_1_TB\r
+      Port ( DEVSELn : In    std_logic;\r
+               INTAn : In    std_logic;\r
+             KONST_1 : In    std_logic;\r
+             PCI_IDSEL : In    std_logic;\r
+             REG_OUT_XX7 : In    std_logic_vector (7 downto 0);\r
+             TB_DEVSELn : Out   std_logic;\r
+             TB_INTAn : Out   std_logic;\r
+             TB_PCI_IDSEL : Out   std_logic );\r
+   end component;\r
+\r
+   component VEN_REV_ID\r
+      Port (  REV_ID : Out   std_logic_vector (7 downto 0);\r
+              VEN_ID : Out   std_logic_vector (15 downto 0) );\r
+   end component;\r
+\r
+   component INTERRUPT\r
+      Port ( INT_IN_0 : In    std_logic;\r
+             INT_IN_1 : In    std_logic;\r
+             INT_IN_2 : In    std_logic;\r
+             INT_IN_3 : In    std_logic;\r
+             INT_IN_4 : In    std_logic;\r
+             INT_IN_5 : In    std_logic;\r
+             INT_IN_6 : In    std_logic;\r
+             INT_IN_7 : In    std_logic;\r
+             INT_MASKE : In    std_logic_vector (7 downto 0);\r
+             INT_RES : In    std_logic_vector (7 downto 0);\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             READ_XX5_4 : In    std_logic;\r
+               RESET : In    std_logic;\r
+             TAST_RESn : In    std_logic;\r
+             TAST_SETn : In    std_logic;\r
+               TRDYn : In    std_logic;\r
+             INT_REG : Out   std_logic_vector (7 downto 0);\r
+               INTAn : Out   std_logic;\r
+             PCI_INTAn : Out   std_logic );\r
+   end component;\r
+\r
+   component FIFO_CONTROL\r
+      Port ( FIFO_RDn : In    std_logic;\r
+             FLAG_IN_0 : In    std_logic;\r
+             FLAG_IN_4 : In    std_logic;\r
+                HOLD : In    std_logic;\r
+             KONST_1 : In    std_logic;\r
+             PCI_CLOCK : In    std_logic;\r
+             PSC_ENABLE : In    std_logic;\r
+               R_EFn : In    std_logic;\r
+               R_FFn : In    std_logic;\r
+               R_HFn : In    std_logic;\r
+               RESET : In    std_logic;\r
+               S_EFn : In    std_logic;\r
+               S_FFn : In    std_logic;\r
+             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
+               S_HFn : In    std_logic;\r
+             SERIAL_IN : In    std_logic;\r
+             SPC_ENABLE : In    std_logic;\r
+             SPC_RDY_IN : In    std_logic;\r
+             WRITE_XX1_0 : In    std_logic;\r
+             R_ERROR : Out   std_logic;\r
+             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
+             R_FIFO_READn : Out   std_logic;\r
+             R_FIFO_RESETn : Out   std_logic;\r
+             R_FIFO_RETRANSMITn : Out   std_logic;\r
+             R_FIFO_WRITEn : Out   std_logic;\r
+             RESERVE : Out   std_logic;\r
+             S_ERROR : Out   std_logic;\r
+             S_FIFO_READn : Out   std_logic;\r
+             S_FIFO_RESETn : Out   std_logic;\r
+             S_FIFO_RETRANSMITn : Out   std_logic;\r
+             S_FIFO_WRITEn : Out   std_logic;\r
+             SERIAL_OUT : Out   std_logic;\r
+             SPC_RDY_OUT : Out   std_logic;\r
+             SR_ERROR : Out   std_logic;\r
+             SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
+   end component;\r
+\r
+   component PCI_TOP\r
+      Port (    FLAG : In    std_logic_vector (7 downto 0);\r
+             INT_REG : In    std_logic_vector (7 downto 0);\r
+             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
+             PCI_CLOCK : In    std_logic;\r
+             PCI_FRAMEn : In    std_logic;\r
+             PCI_IDSEL : In    std_logic;\r
+             PCI_IRDYn : In    std_logic;\r
+             PCI_RSTn : In    std_logic;\r
+             R_FIFO_Q : In    std_logic_vector (7 downto 0);\r
+             REVISON_ID : In    std_logic_vector (7 downto 0);\r
+             VENDOR_ID : In    std_logic_vector (15 downto 0);\r
+              PCI_AD : InOut std_logic_vector (31 downto 0);\r
+             PCI_PAR : InOut std_logic;\r
+              AD_REG : Out   std_logic_vector (31 downto 0);\r
+             DEVSELn : Out   std_logic;\r
+             FIFO_RDn : Out   std_logic;\r
+             PCI_DEVSELn : Out   std_logic;\r
+             PCI_PERRn : Out   std_logic;\r
+             PCI_SERRn : Out   std_logic;\r
+             PCI_STOPn : Out   std_logic;\r
+             PCI_TRDYn : Out   std_logic;\r
+             READ_SEL : Out   std_logic_vector (1 downto 0);\r
+             READ_XX1_0 : Out   std_logic;\r
+             READ_XX3_2 : Out   std_logic;\r
+             READ_XX5_4 : Out   std_logic;\r
+             READ_XX7_6 : Out   std_logic;\r
+             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);\r
+             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);\r
+             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0);\r
+               TRDYn : Out   std_logic;\r
+             WRITE_XX1_0 : Out   std_logic;\r
+             WRITE_XX3_2 : Out   std_logic;\r
+             WRITE_XX5_4 : Out   std_logic;\r
+             WRITE_XX7_6 : Out   std_logic );\r
+   end component;\r
+\r
+begin\r
+\r
+   I19 : MESS_1_TB\r
+      Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
+                 PCI_IDSEL=>PCI_IDSEL,\r
+                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
+                 TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,\r
+                 TB_PCI_IDSEL=>TB_IDSEL );\r
+   I18 : VEN_REV_ID\r
+      Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
+                 VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );\r
+   I16 : INTERRUPT\r
+      Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),\r
+                 INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,\r
+                 INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,\r
+                 INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
+                 INT_RES(7 downto 0)=>AD_REG(7 downto 0),\r
+                 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
+                 READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),\r
+                 TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,\r
+                 TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
+                 INTAn=>INTAn, PCI_INTAn=>PCI_INTAn );\r
+   I14 : FIFO_CONTROL\r
+      Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,\r
+                 FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,\r
+                 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),\r
+                 R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,\r
+                 RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,\r
+                 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
+                 S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,\r
+                 SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,\r
+                 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
+                 R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
+                 R_FIFO_READn=>R_FIFO_READn,\r
+                 R_FIFO_RESETn=>R_FIFO_RESETn,\r
+                 R_FIFO_RETRANSMITn=>R_FIFO_RTn,\r
+                 R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,\r
+                 S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,\r
+                 S_FIFO_RESETn=>S_FIFO_RESETn,\r
+                 S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
+                 S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
+                 SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
+                 SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
+   I1 : PCI_TOP\r
+      Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r
+                 INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
+                 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
+                 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
+                 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
+                 PCI_RSTn=>PCI_RSTn,\r
+                 R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),\r
+                 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
+                 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
+                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
+                 PCI_PAR=>PCI_PAR,\r
+                 AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
+                 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,\r
+                 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,\r
+                 PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,\r
+                 PCI_TRDYn=>PCI_TRDYn,\r
+                 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
+                 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,\r
+                 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,\r
+                 REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),\r
+                 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
+                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
+                 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,\r
+                 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
+                 WRITE_XX7_6=>WRITE_XX7_6 );\r
+\r
+end SCHEMATIC;\r
diff --git a/dhwk/source/user_io.vhd b/dhwk/source/user_io.vhd
new file mode 100644 (file)
index 0000000..72070cd
--- /dev/null
@@ -0,0 +1,129 @@
+-- VHDL model created from schematic user_io.sch -- Jan 09 09:34:12 2007\r
+\r
+\r
+\r
+LIBRARY ieee;\r
+\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+\r
+entity USER_IO is\r
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
+             ADDR_REG : In    std_logic_vector (31 downto 0);\r
+             CBE_REGn : In    std_logic_vector (3 downto 0);\r
+                FLAG : In    std_logic_vector (7 downto 0);\r
+             INT_REG : In    std_logic_vector (7 downto 0);\r
+             IO_WR_COM : In    std_logic;\r
+             IRDY_REGn : In    std_logic;\r
+             PCI_CLK : In    std_logic;\r
+             R_FIFO_Q : In    std_logic_vector (7 downto 0);\r
+             READ_SEL : In    std_logic_vector (1 downto 0);\r
+               TRDYn : In    std_logic;\r
+             READ_XX1_0 : Out   std_logic;\r
+             READ_XX3_2 : Out   std_logic;\r
+             READ_XX5_4 : Out   std_logic;\r
+             READ_XX7_6 : Out   std_logic;\r
+             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);\r
+             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);\r
+             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0);\r
+             USER_DATA_OUT : Out   std_logic_vector (31 downto 0);\r
+             WRITE_XX1_0 : Out   std_logic;\r
+             WRITE_XX3_2 : Out   std_logic;\r
+             WRITE_XX5_4 : Out   std_logic;\r
+             WRITE_XX7_6 : Out   std_logic );\r
+end USER_IO;\r
+\r
+architecture SCHEMATIC of USER_IO is\r
+\r
+   SIGNAL gnd : std_logic := '0';\r
+   SIGNAL vcc : std_logic := '1';\r
+\r
+   signal WRITE_XX1_0_DUMMY : std_logic;\r
+   signal WRITE_XX7_6_DUMMY : std_logic;\r
+   signal REG_OUT_XX7_DUMMY : std_logic_vector (7 downto 0);\r
+   signal REG_OUT_XX6_DUMMY : std_logic_vector (7 downto 0);\r
+   signal REG_OUT_XX0_DUMMY : std_logic_vector (7 downto 0);\r
+\r
+   component IO_WR_SEL\r
+      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);\r
+             CBE_REGn : In    std_logic_vector (3 downto 0);\r
+             IO_WR_COM : In    std_logic;\r
+             IRDY_REGn : In    std_logic;\r
+               TRDYn : In    std_logic;\r
+             WRITE_XX1_0 : Out   std_logic;\r
+             WRITE_XX3_2 : Out   std_logic;\r
+             WRITE_XX5_4 : Out   std_logic;\r
+             WRITE_XX7_6 : Out   std_logic );\r
+   end component;\r
+\r
+   component DATA_MUX\r
+      Port ( ADDR_REG : In    std_logic_vector (31 downto 0);\r
+             CBE_REGn : In    std_logic_vector (3 downto 0);\r
+             MUX_IN_XX0 : In    std_logic_vector (7 downto 0);\r
+             MUX_IN_XX1 : In    std_logic_vector (7 downto 0);\r
+             MUX_IN_XX2 : In    std_logic_vector (7 downto 0);\r
+             MUX_IN_XX3 : In    std_logic_vector (7 downto 0);\r
+             MUX_IN_XX4 : In    std_logic_vector (7 downto 0);\r
+             MUX_IN_XX5 : In    std_logic_vector (7 downto 0);\r
+             MUX_IN_XX6 : In    std_logic_vector (7 downto 0);\r
+             MUX_IN_XX7 : In    std_logic_vector (7 downto 0);\r
+             READ_SEL : In    std_logic_vector (1 downto 0);\r
+             MUX_OUT : Out   std_logic_vector (31 downto 0);\r
+             READ_XX1_0 : Out   std_logic;\r
+             READ_XX3_2 : Out   std_logic;\r
+             READ_XX5_4 : Out   std_logic;\r
+             READ_XX7_6 : Out   std_logic );\r
+   end component;\r
+\r
+   component REG_IO\r
+      Port (  AD_REG : In    std_logic_vector (31 downto 0);\r
+             PCI_CLOCK : In    std_logic;\r
+               RESET : In    std_logic;\r
+             WRITE_XX1_0 : In    std_logic;\r
+             WRITE_XX7_6 : In    std_logic;\r
+             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);\r
+             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);\r
+             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0) );\r
+   end component;\r
+\r
+begin\r
+\r
+   REG_OUT_XX0 <= REG_OUT_XX0_DUMMY;\r
+   REG_OUT_XX6 <= REG_OUT_XX6_DUMMY;\r
+   REG_OUT_XX7 <= REG_OUT_XX7_DUMMY;\r
+   WRITE_XX7_6 <= WRITE_XX7_6_DUMMY;\r
+   WRITE_XX1_0 <= WRITE_XX1_0_DUMMY;\r
+\r
+   I4 : IO_WR_SEL\r
+      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
+                 IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,\r
+                 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0_DUMMY,\r
+                 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
+                 WRITE_XX7_6=>WRITE_XX7_6_DUMMY );\r
+   I2 : DATA_MUX\r
+      Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
+                 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
+                 MUX_IN_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),\r
+                 MUX_IN_XX1(7 downto 0)=>FLAG(7 downto 0),\r
+                 MUX_IN_XX2(7 downto 0)=>R_FIFO_Q(7 downto 0),\r
+                 MUX_IN_XX3(7 downto 0)=>FLAG(7 downto 0),\r
+                 MUX_IN_XX4(7 downto 0)=>INT_REG(7 downto 0),\r
+                 MUX_IN_XX5(7 downto 0)=>FLAG(7 downto 0),\r
+                 MUX_IN_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),\r
+                 MUX_IN_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0),\r
+                 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
+                 MUX_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),\r
+                 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,\r
+                 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6 );\r
+   I1 : REG_IO\r
+      Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
+                 PCI_CLOCK=>PCI_CLK, RESET=>REG_OUT_XX7_DUMMY(0),\r
+                 WRITE_XX1_0=>WRITE_XX1_0_DUMMY,\r
+                 WRITE_XX7_6=>WRITE_XX7_6_DUMMY,\r
+                 REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),\r
+                 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),\r
+                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0) );\r
+\r
+end SCHEMATIC;\r
diff --git a/dhwk/source/verg_8.vhd b/dhwk/source/verg_8.vhd
new file mode 100644 (file)
index 0000000..294aac5
--- /dev/null
@@ -0,0 +1,28 @@
+-- J.STELZNER\r
+-- INFORMATIK-3 LABOR\r
+-- 23.08.2006\r
+-- File: VERG_8.VHD\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+\r
+entity VERG_8 is\r
+       port\r
+       (\r
+       GLEICH                  :in             std_logic_vector(7 downto 0);\r
+       GLEICH_OUT      :out    std_logic\r
+       );\r
+\r
+end entity VERG_8 ;\r
+\r
+architecture VERG_8_DESIGN of VERG_8 is\r
\r
+\r
+begin\r
+\r
+--     GLEICH(0) nicht noetig. Addr-Bereich = 16 Byte\r
+\r
+--     GLEICH_OUT      <=      '1'     when    GLEICH(7 downto 0)      =       "11111111"      else    '0';    \r
+               GLEICH_OUT      <=      '1'     when    GLEICH(7 downto 1)      =       "1111111"               else    '0'; \r
\r
+end architecture VERG_8_DESIGN ;\r
diff --git a/dhwk/source/vergleich.vhd b/dhwk/source/vergleich.vhd
new file mode 100644 (file)
index 0000000..66a9709
--- /dev/null
@@ -0,0 +1,71 @@
+-- VHDL model created from schematic vergleich.sch -- Jan 09 09:34:16 2007\r
+\r
+\r
+\r
+LIBRARY ieee;\r
+\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+\r
+entity VERGLEICH is\r
+      Port (    IN_A : In    std_logic_vector (31 downto 0);\r
+                IN_B : In    std_logic_vector (31 downto 0);\r
+             GLEICH_OUT : Out   std_logic );\r
+end VERGLEICH;\r
+\r
+architecture SCHEMATIC of VERGLEICH is\r
+\r
+   SIGNAL gnd : std_logic := '0';\r
+   SIGNAL vcc : std_logic := '1';\r
+\r
+   signal   GLEICH : std_logic_vector (7 downto 0);\r
+\r
+   component VERG_2\r
+      Port (    IN_A : In    std_logic_vector (1 downto 0);\r
+                IN_B : In    std_logic_vector (1 downto 0);\r
+              GLEICH : Out   std_logic );\r
+   end component;\r
+\r
+   component VERG_8\r
+      Port (  GLEICH : In    std_logic_vector (7 downto 0);\r
+             GLEICH_OUT : Out   std_logic );\r
+   end component;\r
+\r
+   component VERG_4\r
+      Port (    IN_A : In    std_logic_vector (3 downto 0);\r
+                IN_B : In    std_logic_vector (3 downto 0);\r
+              GLEICH : Out   std_logic );\r
+   end component;\r
+\r
+begin\r
+\r
+   I11 : VERG_2\r
+      Port Map ( IN_A(1 downto 0)=>IN_A(3 downto 2),\r
+                 IN_B(1 downto 0)=>IN_B(3 downto 2), GLEICH=>GLEICH(0) );\r
+   I9 : VERG_8\r
+      Port Map ( GLEICH(7 downto 0)=>GLEICH(7 downto 0),\r
+                 GLEICH_OUT=>GLEICH_OUT );\r
+   I8 : VERG_4\r
+      Port Map ( IN_A(3 downto 0)=>IN_A(31 downto 28),\r
+                 IN_B(3 downto 0)=>IN_B(31 downto 28), GLEICH=>GLEICH(7) );\r
+   I7 : VERG_4\r
+      Port Map ( IN_A(3 downto 0)=>IN_A(27 downto 24),\r
+                 IN_B(3 downto 0)=>IN_B(27 downto 24), GLEICH=>GLEICH(6) );\r
+   I6 : VERG_4\r
+      Port Map ( IN_A(3 downto 0)=>IN_A(23 downto 20),\r
+                 IN_B(3 downto 0)=>IN_B(23 downto 20), GLEICH=>GLEICH(5) );\r
+   I5 : VERG_4\r
+      Port Map ( IN_A(3 downto 0)=>IN_A(19 downto 16),\r
+                 IN_B(3 downto 0)=>IN_B(19 downto 16), GLEICH=>GLEICH(4) );\r
+   I4 : VERG_4\r
+      Port Map ( IN_A(3 downto 0)=>IN_A(15 downto 12),\r
+                 IN_B(3 downto 0)=>IN_B(15 downto 12), GLEICH=>GLEICH(3) );\r
+   I3 : VERG_4\r
+      Port Map ( IN_A(3 downto 0)=>IN_A(11 downto 8),\r
+                 IN_B(3 downto 0)=>IN_B(11 downto 8), GLEICH=>GLEICH(2) );\r
+   I2 : VERG_4\r
+      Port Map ( IN_A(3 downto 0)=>IN_A(7 downto 4),\r
+                 IN_B(3 downto 0)=>IN_B(7 downto 4), GLEICH=>GLEICH(1) );\r
+\r
+end SCHEMATIC;\r
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