git.zerfleddert.de Git - raggedstone/blob - ethernet/source/top.vhd

   1 LIBRARY ieee;
   2 USE ieee.std_logic_1164.ALL;
   3
   4 entity ethernet is
   5 PORT(
   6         PCI_AD : INOUT std_logic_vector(31 downto 0);
   7         PCI_CLOCK : IN std_logic;
   8         PCI_IDSEL : IN std_logic;
   9         PCI_CBEn : INOUT std_logic_vector (3 downto 0);
  10         PCI_FRAMEn : INOUT std_logic;
  11         PCI_IRDYn : INOUT std_logic;
  12         PCI_RSTn : INOUT std_logic;
  13         PCI_DEVSELn : INOUT std_logic;
  14         PCI_INTAn : INOUT std_logic;
  15         PCI_PERRn : INOUT std_logic;
  16         PCI_SERRn : INOUT std_logic;
  17         PCI_STOPn : INOUT std_logic;
  18         PCI_TRDYn : INOUT std_logic;
  19         PCI_PAR   : INOUT std_logic;
  20         PCI_REQn  : OUT std_logic;
  21         PCI_GNTn : IN std_logic;
  22
  23         MTX_CLK_PAD_I : IN std_logic;
  24         MTXD_PAD_O : OUT std_logic_vector (3 downto 0);
  25         MTXEN_PAD_O : OUT std_logic;
  26         MRX_CLK_PAD_I : IN std_logic;
  27         MRXD_PAD_I : IN std_logic_vector (3 downto 0);
  28         MRXDV_PAD_I : IN std_logic;
  29         MRXERR_PAD_I : IN std_logic;
  30         MCOLL_PAD_I : IN std_logic;
  31         MCRS_PAD_I : IN std_logic;
  32         MD_PAD_IO : INOUT std_logic;
  33         MDC_PAD_O : OUT std_logic
  34 );
  35 end ethernet;
  36
  37 architecture ethernet_arch of ethernet is
  38
  39 COMPONENT eth_top
  40 PORT(
  41         wb_clk_i : IN std_logic;
  42         wb_rst_i : IN std_logic;
  43         wb_dat_i : IN std_logic_vector(31 downto 0);
  44         wb_adr_i : IN std_logic_vector(11 downto 2);
  45         wb_sel_i : IN std_logic_vector(3 downto 0);
  46         wb_we_i : IN std_logic;
  47         wb_cyc_i : IN std_logic;
  48         wb_stb_i : IN std_logic;
  49         m_wb_dat_i : IN std_logic_vector(31 downto 0);
  50         m_wb_ack_i : IN std_logic;
  51         m_wb_err_i : IN std_logic;
  52         mtx_clk_pad_i : IN std_logic;
  53         mrx_clk_pad_i : IN std_logic;
  54         mrxd_pad_i : IN std_logic_vector(3 downto 0);
  55         mrxdv_pad_i : IN std_logic;
  56         mrxerr_pad_i : IN std_logic;
  57         mcoll_pad_i : IN std_logic;
  58         mcrs_pad_i : IN std_logic;
  59         md_pad_i : IN std_logic;
  60         wb_dat_o : OUT std_logic_vector(31 downto 0);
  61         wb_ack_o : OUT std_logic;
  62         wb_err_o : OUT std_logic;
  63         m_wb_adr_o : OUT std_logic_vector(31 downto 0);
  64         m_wb_sel_o : OUT std_logic_vector(3 downto 0);
  65         m_wb_we_o : OUT std_logic;
  66         m_wb_dat_o : OUT std_logic_vector(31 downto 0);
  67         m_wb_cyc_o : OUT std_logic;
  68         m_wb_stb_o : OUT std_logic;
  69         mtxd_pad_o : OUT std_logic_vector(3 downto 0);
  70         mtxen_pad_o : OUT std_logic;
  71         mtxerr_pad_o : OUT std_logic;
  72         mdc_pad_o : OUT std_logic;
  73         md_pad_o : OUT std_logic;
  74         md_padoe_o : OUT std_logic;
  75         int_o : OUT std_logic
  76         );
  77 END COMPONENT;
  78
  79 COMPONENT pci_bridge32
  80 PORT(
  81         wb_clk_i : IN std_logic;
  82         wb_rst_i : IN std_logic;
  83         wb_int_i : IN std_logic;
  84         wbs_adr_i : IN std_logic_vector(31 downto 0);
  85         wbs_dat_i : IN std_logic_vector(31 downto 0);
  86         wbs_sel_i : IN std_logic_vector(3 downto 0);
  87         wbs_cyc_i : IN std_logic;
  88         wbs_stb_i : IN std_logic;
  89         wbs_we_i : IN std_logic;
  90         wbs_cti_i : IN std_logic_vector(2 downto 0);
  91         wbs_bte_i : IN std_logic_vector(1 downto 0);
  92         wbm_dat_i : IN std_logic_vector(31 downto 0);
  93         wbm_ack_i : IN std_logic;
  94         wbm_rty_i : IN std_logic;
  95         wbm_err_i : IN std_logic;
  96         pci_clk_i : IN std_logic;
  97         pci_rst_i : IN std_logic;
  98         pci_inta_i : IN std_logic;
  99         pci_gnt_i : IN std_logic;
 100         pci_frame_i : IN std_logic;
 101         pci_irdy_i : IN std_logic;
 102         pci_idsel_i : IN std_logic;
 103         pci_devsel_i : IN std_logic;
 104         pci_trdy_i : IN std_logic;
 105         pci_stop_i : IN std_logic;
 106         pci_ad_i : IN std_logic_vector(31 downto 0);
 107         pci_cbe_i : IN std_logic_vector(3 downto 0);
 108         pci_par_i : IN std_logic;
 109         pci_perr_i : IN std_logic;
 110         wb_rst_o : OUT std_logic;
 111         wb_int_o : OUT std_logic;
 112         wbs_dat_o : OUT std_logic_vector(31 downto 0);
 113         wbs_ack_o : OUT std_logic;
 114         wbs_rty_o : OUT std_logic;
 115         wbs_err_o : OUT std_logic;
 116         wbm_adr_o : OUT std_logic_vector(31 downto 0);
 117         wbm_dat_o : OUT std_logic_vector(31 downto 0);
 118         wbm_sel_o : OUT std_logic_vector(3 downto 0);
 119         wbm_cyc_o : OUT std_logic;
 120         wbm_stb_o : OUT std_logic;
 121         wbm_we_o : OUT std_logic;
 122         wbm_cti_o : OUT std_logic_vector(2 downto 0);
 123         wbm_bte_o : OUT std_logic_vector(1 downto 0);
 124         pci_rst_o : OUT std_logic;
 125         pci_inta_o : OUT std_logic;
 126         pci_rst_oe_o : OUT std_logic;
 127         pci_inta_oe_o : OUT std_logic;
 128         pci_req_o : OUT std_logic;
 129         pci_req_oe_o : OUT std_logic;
 130         pci_frame_o : OUT std_logic;
 131         pci_frame_oe_o : OUT std_logic;
 132         pci_irdy_oe_o : OUT std_logic;
 133         pci_devsel_oe_o : OUT std_logic;
 134         pci_trdy_oe_o : OUT std_logic;
 135         pci_stop_oe_o : OUT std_logic;
 136         pci_ad_oe_o : OUT std_logic_vector(31 downto 0);
 137         pci_cbe_oe_o : OUT std_logic_vector(3 downto 0);
 138         pci_irdy_o : OUT std_logic;
 139         pci_devsel_o : OUT std_logic;
 140         pci_trdy_o : OUT std_logic;
 141         pci_stop_o : OUT std_logic;
 142         pci_ad_o : OUT std_logic_vector(31 downto 0);
 143         pci_cbe_o : OUT std_logic_vector(3 downto 0);
 144         pci_par_o : OUT std_logic;
 145         pci_par_oe_o : OUT std_logic;
 146         pci_perr_o : OUT std_logic;
 147         pci_perr_oe_o : OUT std_logic;
 148         pci_serr_o : OUT std_logic;
 149         pci_serr_oe_o : OUT std_logic
 150         );
 151 END COMPONENT;
 152
 153 signal pci_rst_o : std_logic;
 154 signal pci_rst_oe_o : std_logic;
 155 signal pci_inta_o : std_logic;
 156 signal pci_inta_oe_o : std_logic;
 157 signal pci_req_o : std_logic;
 158 signal pci_req_oe_o : std_logic;
 159 signal pci_frame_o : std_logic;
 160 signal pci_frame_oe_o : std_logic;
 161 signal pci_irdy_o : std_logic;
 162 signal pci_irdy_oe_o : std_logic;
 163 signal pci_devsel_o : std_logic;
 164 signal pci_devsel_oe_o : std_logic;
 165 signal pci_trdy_o : std_logic;
 166 signal pci_trdy_oe_o : std_logic;
 167 signal pci_stop_o : std_logic;
 168 signal pci_stop_oe_o : std_logic;
 169 signal pci_par_o : std_logic;
 170 signal pci_par_oe_o : std_logic;
 171 signal pci_perr_o : std_logic;
 172 signal pci_perr_oe_o : std_logic;
 173 signal pci_serr_o : std_logic;
 174 signal pci_serr_oe_o : std_logic;
 175 signal pci_ad_oe_o : std_logic_vector(31 downto 0);
 176 signal pci_cbe_oe_o : std_logic_vector(3 downto 0);
 177 signal pci_ad_o : std_logic_vector (31 downto 0);
 178 signal pci_cbe_o : std_logic_vector (3 downto 0);
 179
 180 signal wb_clk_i : std_logic;
 181 signal wb_rst_i : std_logic;
 182 signal wb_dat_i : std_logic_vector (31 downto 0);
 183 signal wb_dat_o : std_logic_vector (31 downto 0);
 184 signal wb_adr_i : std_logic_vector (11 downto 2);
 185 signal wb_sel_i : std_logic_vector (3 downto 0);
 186 signal wb_we_i : std_logic;
 187 signal wb_cyc_i : std_logic;
 188 signal wb_stb_i : std_logic;
 189 signal wb_ack_o : std_logic;
 190 signal wb_err_o : std_logic;
 191 signal m_wb_adr_o : std_logic_vector(31 downto 0);
 192 signal m_wb_sel_o : std_logic_vector(3 downto 0);
 193 signal m_wb_we_o : std_logic;
 194 signal m_wb_dat_o : std_logic_vector(31 downto 0);
 195 signal m_wb_dat_i : std_logic_vector(31 downto 0);
 196 signal m_wb_cyc_o : std_logic;
 197 signal m_wb_stb_o : std_logic;
 198 signal m_wb_ack_i : std_logic;
 199 signal m_wb_err_i : std_logic;
 200 signal md_pad_o : std_logic;
 201 signal md_padoe_o : std_logic;
 202 signal int_o : std_logic;
 203 signal wbm_adr_o : std_logic_vector(31 downto 0);
 204
 205 BEGIN
 206
 207 PCI_RSTn    <= pci_rst_o    when (pci_rst_oe_o = '1')     else 'Z';
 208 PCI_INTAn   <= pci_inta_o   when (pci_inta_oe_o = '1')    else 'Z';
 209 PCI_REQn    <= pci_req_o    when (pci_req_oe_o = '1')     else 'Z';
 210 PCI_FRAMEn  <= pci_frame_o  when (pci_frame_oe_o = '1')     else 'Z';
 211 PCI_IRDYn   <= pci_irdy_o   when (pci_irdy_oe_o = '1')    else 'Z';
 212 PCI_DEVSELn <= pci_devsel_o when (pci_devsel_oe_o = '1')  else 'Z';
 213 PCI_TRDYn   <= pci_trdy_o   when (pci_trdy_oe_o = '1')    else 'Z';
 214 PCI_STOPn   <= pci_stop_o   when (pci_stop_oe_o = '1')    else 'Z';
 215 PCI_PAR     <= pci_par_o    when (pci_par_oe_o = '1')     else 'Z';
 216 PCI_PERRn   <= pci_perr_o   when (pci_perr_oe_o = '1')    else 'Z';
 217 PCI_SERRn   <= pci_serr_o   when (pci_serr_oe_o = '1')    else 'Z';
 218 MD_PAD_IO   <= md_pad_o     when (md_padoe_o = '1')       else 'Z';
 219
 220 BLA1: FOR i in 31 downto 0 generate
 221 PCI_AD(i) <= pci_ad_o(i) when (pci_ad_oe_o(i) = '1') else 'Z';
 222 end generate;
 223
 224 BLA2: FOR i in 3 downto 0 generate
 225 PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z';
 226 end generate;
 227
 228 wb_adr_i <= wbm_adr_o (11 downto 2);
 229
 230 Inst_pci_bridge32: pci_bridge32 PORT MAP(
 231         wb_clk_i => wb_clk_i ,
 232         wb_rst_i => '0',
 233         wb_rst_o => wb_rst_i,
 234         wb_int_i => int_o,
 235         -- wb_int_o => ,
 236         wbs_adr_i => m_wb_adr_o ,
 237         wbs_dat_i => m_wb_dat_o,
 238         wbs_dat_o => m_wb_dat_i,
 239         wbs_sel_i => m_wb_sel_o,
 240         wbs_cyc_i => m_wb_cyc_o,
 241         wbs_stb_i => m_wb_stb_o,
 242         wbs_we_i => m_wb_we_o,
 243         wbs_cti_i => (others => '0'),
 244         wbs_bte_i => (others => '0'),
 245         wbs_ack_o => m_wb_ack_i,
 246         -- wbs_rty_o => ,
 247         wbs_err_o => m_wb_err_i,
 248         wbm_adr_o => wbm_adr_o,
 249         wbm_dat_i => wb_dat_o,
 250         wbm_dat_o => wb_dat_i,
 251         wbm_sel_o => wb_sel_i,
 252         wbm_cyc_o => wb_cyc_i,
 253         wbm_stb_o => wb_stb_i,
 254         wbm_we_o => wb_we_i,
 255         -- wbm_cti_o => ,
 256         -- wbm_bte_o => ,
 257         wbm_ack_i => wb_ack_o ,
 258         wbm_rty_i => '0',
 259         wbm_err_i => wb_err_o,
 260         pci_clk_i => PCI_CLOCK,
 261         pci_rst_i => PCI_RSTn,
 262         pci_rst_o => pci_rst_o ,
 263         pci_rst_oe_o => pci_rst_oe_o,
 264         pci_inta_i => PCI_INTAn,
 265         pci_inta_o => pci_inta_o,
 266         pci_inta_oe_o => pci_inta_oe_o,
 267         pci_req_o => pci_req_o,
 268         pci_req_oe_o => pci_req_oe_o,
 269         pci_gnt_i => PCI_GNTn,
 270         pci_frame_i => PCI_FRAMEn,
 271         pci_frame_o => pci_frame_o,
 272         pci_frame_oe_o => pci_frame_oe_o,
 273         pci_irdy_oe_o => pci_irdy_oe_o,
 274         pci_devsel_oe_o => pci_devsel_oe_o,
 275         pci_trdy_oe_o => pci_trdy_oe_o,
 276         pci_stop_oe_o => pci_stop_oe_o,
 277         pci_ad_oe_o => pci_ad_oe_o,
 278         pci_cbe_oe_o => pci_cbe_oe_o,
 279         pci_irdy_i => PCI_IRDYn,
 280         pci_irdy_o => pci_irdy_o,
 281         pci_idsel_i => PCI_IDSEL,
 282         pci_devsel_i => PCI_DEVSELn,
 283         pci_devsel_o => pci_devsel_o,
 284         pci_trdy_i => PCI_TRDYn,
 285         pci_trdy_o => pci_trdy_o,
 286         pci_stop_i => PCI_STOPn,
 287         pci_stop_o => pci_stop_o,
 288         pci_ad_i => PCI_AD,
 289         pci_ad_o => pci_ad_o,
 290         pci_cbe_i => PCI_CBEn,
 291         pci_cbe_o => pci_cbe_o,
 292         pci_par_i => PCI_PAR,
 293         pci_par_o => pci_par_o,
 294         pci_par_oe_o => pci_par_oe_o,
 295         pci_perr_i => PCI_PERRn,
 296         pci_perr_o => pci_perr_o,
 297         pci_perr_oe_o => pci_perr_oe_o,
 298         pci_serr_o => pci_serr_o,
 299         pci_serr_oe_o =>  pci_serr_oe_o
 300 );
 301
 302 Inst_eth_top: eth_top PORT MAP(
 303         wb_clk_i   => wb_clk_i  ,
 304         wb_rst_i   => wb_rst_i  ,
 305         wb_dat_i   => wb_dat_i  ,
 306         wb_dat_o   => wb_dat_o  ,
 307         wb_adr_i   => wb_adr_i  ,
 308         wb_sel_i   => wb_sel_i  ,
 309         wb_we_i    => wb_we_i   ,
 310         wb_cyc_i   => wb_cyc_i  ,
 311         wb_stb_i   => wb_stb_i  ,
 312         wb_ack_o   => wb_ack_o  ,
 313         wb_err_o   => wb_err_o  ,
 314         m_wb_adr_o => m_wb_adr_o,
 315         m_wb_sel_o => m_wb_sel_o,
 316         m_wb_we_o  => m_wb_we_o ,
 317         m_wb_dat_o => m_wb_dat_o,
 318         m_wb_dat_i => m_wb_dat_i,
 319         m_wb_cyc_o => m_wb_cyc_o,
 320         m_wb_stb_o => m_wb_stb_o,
 321         m_wb_ack_i => m_wb_ack_i,
 322         m_wb_err_i => m_wb_err_i,
 323         mtx_clk_pad_i => MTX_CLK_PAD_I,
 324         mtxd_pad_o => MTXD_PAD_O,
 325         mtxen_pad_o => MTXEN_PAD_O,
 326         -- mtxerr_pad_o => ,
 327         mrx_clk_pad_i => MRX_CLK_PAD_I,
 328         mrxd_pad_i => MRXD_PAD_I,
 329         mrxdv_pad_i => MRXDV_PAD_I,
 330         mrxerr_pad_i => MRXERR_PAD_I,
 331         mcoll_pad_i => MCOLL_PAD_I,
 332         mcrs_pad_i => MCRS_PAD_I,
 333         mdc_pad_o => MDC_PAD_O,
 334         md_pad_i => MD_PAD_IO,
 335         md_pad_o => md_pad_o,
 336         md_padoe_o => md_padoe_o,
 337         int_o => int_o
 338 );
 339
 340 end architecture ethernet_arch;