1 //////////////////////////////////////////////////////////////////////
3 //// eth_spram_256x32.v ////
5 //// This file is part of the Ethernet IP core project ////
6 //// http://www.opencores.org/projects/ethmac/ ////
9 //// - Igor Mohor (igorM@opencores.org) ////
11 //// All additional information is available in the Readme.txt ////
14 //////////////////////////////////////////////////////////////////////
16 //// Copyright (C) 2001, 2002 Authors ////
18 //// This source file may be used and distributed without ////
19 //// restriction provided that this copyright statement is not ////
20 //// removed from the file and that any derivative work contains ////
21 //// the original copyright notice and the associated disclaimer. ////
23 //// This source file is free software; you can redistribute it ////
24 //// and/or modify it under the terms of the GNU Lesser General ////
25 //// Public License as published by the Free Software Foundation; ////
26 //// either version 2.1 of the License, or (at your option) any ////
27 //// later version. ////
29 //// This source is distributed in the hope that it will be ////
30 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
31 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
32 //// PURPOSE. See the GNU Lesser General Public License for more ////
35 //// You should have received a copy of the GNU Lesser General ////
36 //// Public License along with this source; if not, download it ////
37 //// from http://www.opencores.org/lgpl.shtml ////
39 //////////////////////////////////////////////////////////////////////
41 // CVS Revision History
43 // $Log: eth_spram_256x32.v,v $
44 // Revision 1.1 2007-03-20 17:50:56 sithglan
47 // Revision 1.10 2005/02/21 12:48:07 igorm
50 // Revision 1.9 2003/12/05 12:43:06 tadejm
51 // Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.
53 // Revision 1.8 2003/12/04 14:59:13 simons
54 // Lapsus fixed (!we -> ~we).
56 // Revision 1.7 2003/11/12 18:24:59 tadejm
57 // WISHBONE slave changed and tested from only 32-bit accesss to byte access.
59 // Revision 1.6 2003/10/17 07:46:15 markom
60 // mbist signals updated according to newest convention
62 // Revision 1.5 2003/08/14 16:42:58 simons
63 // Artisan ram instance added.
65 // Revision 1.4 2002/10/18 17:04:20 tadejm
66 // Changed BIST scan signals.
68 // Revision 1.3 2002/10/10 16:29:30 mohor
71 // Revision 1.2 2002/09/23 18:24:31 mohor
72 // ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
74 // Revision 1.1 2002/07/23 16:36:09 mohor
75 // ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
80 `include "eth_defines.v"
81 `include "timescale.v"
83 module eth_spram_256x32(
84 // Generic synchronous single-port RAM interface
85 clk, rst, ce, we, oe, addr, di, do
89 // debug chain signals
90 mbist_si_i, // bist scan serial in
91 mbist_so_o, // bist scan serial out
92 mbist_ctrl_i // bist chain shift control
100 // Generic synchronous single-port RAM interface
102 input clk; // Clock, rising edge
103 input rst; // Reset, active high
104 input ce; // Chip enable input, active high
105 input [3:0] we; // Write enable input, active high
106 input oe; // Output enable input, active high
107 input [7:0] addr; // address bus inputs
108 input [31:0] di; // input data bus
109 output [31:0] do; // output data bus
113 input mbist_si_i; // bist scan serial in
114 output mbist_so_o; // bist scan serial out
115 input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
118 `ifdef ETH_XILINX_RAMB4
145 .ADDR ({1'b0, addr}),
156 .ADDR ({1'b0, addr}),
167 .ADDR ({1'b0, addr}),
178 .ADDR ({1'b0, addr}),
186 `else // !ETH_XILINX_RAMB4
187 `ifdef ETH_VIRTUAL_SILICON_RAM
189 //vs_hdsp_256x32_bist ram0_bist
190 vs_hdsp_256x32_bw_bist ram0_bist
192 //vs_hdsp_256x32 ram0
193 vs_hdsp_256x32_bw ram0
206 // debug chain signals
207 .mbist_si_i (mbist_si_i),
208 .mbist_so_o (mbist_so_o),
209 .mbist_ctrl_i (mbist_ctrl_i)
213 `else // !ETH_VIRTUAL_SILICON_RAM
215 `ifdef ETH_ARTISAN_RAM
217 //art_hssp_256x32_bist ram0_bist
218 art_hssp_256x32_bw_bist ram0_bist
220 //art_hssp_256x32 ram0
221 art_hssp_256x32_bw ram0
234 // debug chain signals
235 .mbist_si_i (mbist_si_i),
236 .mbist_so_o (mbist_so_o),
237 .mbist_ctrl_i (mbist_ctrl_i)
241 `else // !ETH_ARTISAN_RAM
242 `ifdef ETH_ALTERA_ALTSYNCRAM
244 altera_spram_256x32 altera_spram_256x32_inst
251 ); //exemplar attribute altera_spram_256x32_inst NOOPT TRUE
253 `else // !ETH_ALTERA_ALTSYNCRAM
257 // Generic single-port synchronous RAM model
261 // Generic RAM's registers and wires
263 reg [ 7: 0] mem0 [255:0]; // RAM content
264 reg [15: 8] mem1 [255:0]; // RAM content
265 reg [23:16] mem2 [255:0]; // RAM content
266 reg [31:24] mem3 [255:0]; // RAM content
267 wire [31:0] q; // RAM output
268 reg [7:0] raddr; // RAM read address
270 // Data output drivers
272 assign do = (oe & ce) ? q : {32{1'bz}};
275 // RAM read and write
281 raddr <= #1 addr; // read address needs to be registered to read clock
283 assign #1 q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]};
289 mem3[addr] <= #1 di[31:24];
291 mem2[addr] <= #1 di[23:16];
293 mem1[addr] <= #1 di[15: 8];
295 mem0[addr] <= #1 di[ 7: 0];
298 // Task prints range of memory
299 // *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
305 for (rnum=start;rnum<=finish;rnum=rnum+1)
306 $display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
310 `endif // !ETH_ALTERA_ALTSYNCRAM
311 `endif // !ETH_ARTISAN_RAM
312 `endif // !ETH_VIRTUAL_SILICON_RAM
313 `endif // !ETH_XILINX_RAMB4