1 //////////////////////////////////////////////////////////////////////
3 //// eth_txstatem.v ////
5 //// This file is part of the Ethernet IP core project ////
6 //// http://www.opencores.org/projects/ethmac/ ////
9 //// - Igor Mohor (igorM@opencores.org) ////
10 //// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
11 //// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
13 //// All additional information is avaliable in the Readme.txt ////
16 //////////////////////////////////////////////////////////////////////
18 //// Copyright (C) 2001 Authors ////
20 //// This source file may be used and distributed without ////
21 //// restriction provided that this copyright statement is not ////
22 //// removed from the file and that any derivative work contains ////
23 //// the original copyright notice and the associated disclaimer. ////
25 //// This source file is free software; you can redistribute it ////
26 //// and/or modify it under the terms of the GNU Lesser General ////
27 //// Public License as published by the Free Software Foundation; ////
28 //// either version 2.1 of the License, or (at your option) any ////
29 //// later version. ////
31 //// This source is distributed in the hope that it will be ////
32 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
33 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
34 //// PURPOSE. See the GNU Lesser General Public License for more ////
37 //// You should have received a copy of the GNU Lesser General ////
38 //// Public License along with this source; if not, download it ////
39 //// from http://www.opencores.org/lgpl.shtml ////
41 //////////////////////////////////////////////////////////////////////
43 // CVS Revision History
45 // $Log: eth_txstatem.v,v $
46 // Revision 1.1 2007-03-20 17:50:56 sithglan
49 // Revision 1.6 2003/01/30 13:29:08 tadejm
50 // Defer indication changed.
52 // Revision 1.5 2002/10/30 12:54:50 mohor
53 // State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.
55 // Revision 1.4 2002/01/23 10:28:16 mohor
56 // Link in the header changed.
58 // Revision 1.3 2001/10/19 08:43:51 mohor
59 // eth_timescale.v changed to timescale.v This is done because of the
60 // simulation of the few cores in a one joined project.
62 // Revision 1.2 2001/09/11 14:17:00 mohor
63 // Few little NCSIM warnings fixed.
65 // Revision 1.1 2001/08/06 14:44:29 mohor
66 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
67 // Include files fixed to contain no path.
68 // File names and module names changed ta have a eth_ prologue in the name.
69 // File eth_timescale.v is used to define timescale
70 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
71 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
72 // and Mdo_OE. The bidirectional signal must be created on the top level. This
73 // is done due to the ASIC tools.
75 // Revision 1.1 2001/07/30 21:23:42 mohor
76 // Directory structure changed. Files checked and joind together.
78 // Revision 1.3 2001/06/19 18:16:40 mohor
79 // TxClk changed to MTxClk (as discribed in the documentation).
80 // Crc changed so only one file can be used instead of two.
82 // Revision 1.2 2001/06/19 10:38:07 mohor
83 // Minor changes in header.
85 // Revision 1.1 2001/06/19 10:27:57 mohor
86 // TxEthMAC initial release.
93 `include "timescale.v"
96 module eth_txstatem (MTxClk, Reset, ExcessiveDefer, CarrierSense, NibCnt, IPGT, IPGR1,
97 IPGR2, FullD, TxStartFrm, TxEndFrm, TxUnderRun, Collision, UnderRun,
98 StartTxDone, TooBig, NibCntEq7, NibCntEq15, MaxFrame, Pad, CrcEn,
99 NibbleMinFl, RandomEq0, ColWindow, RetryMax, NoBckof, RandomEqByteCnt,
100 StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS,
101 StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam,
102 StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG
109 input ExcessiveDefer;
133 input RandomEqByteCnt;
136 output StateIdle; // Idle state
137 output StateIPG; // IPG state
138 output StatePreamble; // Preamble state
139 output [1:0] StateData; // Data state
140 output StatePAD; // PAD state
141 output StateFCS; // FCS state
142 output StateJam; // Jam state
143 output StateJam_q; // Delayed Jam state
144 output StateBackOff; // Backoff state
145 output StateDefer; // Defer state
147 output StartFCS; // FCS state will be activated in next clock
148 output StartJam; // Jam state will be activated in next clock
149 output StartBackoff; // Backoff state will be activated in next clock
150 output StartDefer; // Defer state will be activated in next clock
151 output DeferIndication;
152 output StartPreamble; // Preamble state will be activated in next clock
153 output [1:0] StartData; // Data state will be activated in next clock
154 output StartIPG; // IPG state will be activated in next clock
156 wire StartIdle; // Idle state will be activated in next clock
157 wire StartPAD; // PAD state will be activated in next clock
173 // Defining the next state
174 assign StartIPG = StateDefer & ~ExcessiveDefer & ~CarrierSense;
176 assign StartIdle = StateIPG & (Rule1 & NibCnt[6:0] >= IPGT | ~Rule1 & NibCnt[6:0] >= IPGR2);
178 assign StartPreamble = StateIdle & TxStartFrm & ~CarrierSense;
180 assign StartData[0] = ~Collision & (StatePreamble & NibCntEq15 | StateData[1] & ~TxEndFrm);
182 assign StartData[1] = ~Collision & StateData[0] & ~TxUnderRun & ~MaxFrame;
184 assign StartPAD = ~Collision & StateData[1] & TxEndFrm & Pad & ~NibbleMinFl;
186 assign StartFCS = ~Collision & StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & CrcEn
187 | ~Collision & StatePAD & NibbleMinFl & CrcEn;
189 assign StartJam = (Collision | UnderRun) & ((StatePreamble & NibCntEq15) | (|StateData[1:0]) | StatePAD | StateFCS);
191 assign StartBackoff = StateJam & ~RandomEq0 & ColWindow & ~RetryMax & NibCntEq7 & ~NoBckof;
193 assign StartDefer = StateIPG & ~Rule1 & CarrierSense & NibCnt[6:0] <= IPGR1 & NibCnt[6:0] != IPGR2
194 | StateIdle & CarrierSense
195 | StateJam & NibCntEq7 & (NoBckof | RandomEq0 | ~ColWindow | RetryMax)
196 | StateBackOff & (TxUnderRun | RandomEqByteCnt)
197 | StartTxDone | TooBig;
199 assign DeferIndication = StateIdle & CarrierSense;
202 always @ (posedge MTxClk or posedge Reset)
206 StateIPG <= #Tp 1'b0;
207 StateIdle <= #Tp 1'b0;
208 StatePreamble <= #Tp 1'b0;
209 StateData[1:0] <= #Tp 2'b0;
210 StatePAD <= #Tp 1'b0;
211 StateFCS <= #Tp 1'b0;
212 StateJam <= #Tp 1'b0;
213 StateJam_q <= #Tp 1'b0;
214 StateBackOff <= #Tp 1'b0;
215 StateDefer <= #Tp 1'b1;
219 StateData[1:0] <= #Tp StartData[1:0];
220 StateJam_q <= #Tp StateJam;
222 if(StartDefer | StartIdle)
223 StateIPG <= #Tp 1'b0;
226 StateIPG <= #Tp 1'b1;
228 if(StartDefer | StartPreamble)
229 StateIdle <= #Tp 1'b0;
232 StateIdle <= #Tp 1'b1;
234 if(StartData[0] | StartJam)
235 StatePreamble <= #Tp 1'b0;
238 StatePreamble <= #Tp 1'b1;
240 if(StartFCS | StartJam)
241 StatePAD <= #Tp 1'b0;
244 StatePAD <= #Tp 1'b1;
246 if(StartJam | StartDefer)
247 StateFCS <= #Tp 1'b0;
250 StateFCS <= #Tp 1'b1;
252 if(StartBackoff | StartDefer)
253 StateJam <= #Tp 1'b0;
256 StateJam <= #Tp 1'b1;
259 StateBackOff <= #Tp 1'b0;
262 StateBackOff <= #Tp 1'b1;
265 StateDefer <= #Tp 1'b0;
268 StateDefer <= #Tp 1'b1;
273 // This sections defines which interpack gap rule to use
274 always @ (posedge MTxClk or posedge Reset)
280 if(StateIdle | StateBackOff)
283 if(StatePreamble | FullD)