chipscope
[raggedstone] / dhwk / source / top.vhd
1 -- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007
2
3
4
5 LIBRARY ieee;
6
7 USE ieee.std_logic_1164.ALL;
8 USE ieee.numeric_std.ALL;
9
10
11 entity dhwk is
12 Port ( KONST_1 : In std_logic;
13 PCI_CBEn : In std_logic_vector (3 downto 0);
14 PCI_CLOCK : In std_logic;
15 PCI_FRAMEn : In std_logic;
16 PCI_IDSEL : In std_logic;
17 PCI_IRDYn : In std_logic;
18 PCI_RSTn : In std_logic;
19 -- SERIAL_IN : In std_logic;
20 -- SPC_RDY_IN : In std_logic;
21 TAST_RESn : In std_logic;
22 TAST_SETn : In std_logic;
23 LED_2 : out std_logic;
24 LED_3 : out std_logic;
25 LED_4 : out std_logic;
26 LED_5 : out std_logic;
27 PCI_AD : InOut std_logic_vector (31 downto 0);
28 PCI_PAR : InOut std_logic;
29 PCI_DEVSELn : Out std_logic;
30 PCI_INTAn : Out std_logic;
31 PCI_PERRn : Out std_logic;
32 PCI_SERRn : Out std_logic;
33 PCI_STOPn : Out std_logic;
34 PCI_TRDYn : Out std_logic;
35 -- SERIAL_OUT : Out std_logic;
36 -- SPC_RDY_OUT : Out std_logic;
37 TB_IDSEL : Out std_logic;
38 TB_nDEVSEL : Out std_logic;
39 TB_nINTA : Out std_logic );
40 end dhwk;
41
42 architecture SCHEMATIC of dhwk is
43
44 SIGNAL gnd : std_logic := '0';
45 SIGNAL vcc : std_logic := '1';
46
47 signal READ_XX7_6 : std_logic;
48 signal RESERVE : std_logic;
49 signal SR_ERROR : std_logic;
50 signal R_ERROR : std_logic;
51 signal S_ERROR : std_logic;
52 signal WRITE_XX3_2 : std_logic;
53 signal WRITE_XX5_4 : std_logic;
54 signal WRITE_XX7_6 : std_logic;
55 signal READ_XX1_0 : std_logic;
56 signal READ_XX3_2 : std_logic;
57 signal INTAn : std_logic;
58 signal TRDYn : std_logic;
59 signal READ_XX5_4 : std_logic;
60 signal DEVSELn : std_logic;
61 signal FIFO_RDn : std_logic;
62 signal WRITE_XX1_0 : std_logic;
63 signal REG_OUT_XX6 : std_logic_vector (7 downto 0);
64 signal SYNC_FLAG : std_logic_vector (7 downto 0);
65 signal INT_REG : std_logic_vector (7 downto 0);
66 signal REVISON_ID : std_logic_vector (7 downto 0);
67 signal VENDOR_ID : std_logic_vector (15 downto 0);
68 signal READ_SEL : std_logic_vector (1 downto 0);
69 signal AD_REG : std_logic_vector (31 downto 0);
70 signal REG_OUT_XX7 : std_logic_vector (7 downto 0);
71 signal R_EFn : std_logic;
72 signal R_FFn : std_logic;
73 signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);
74 signal R_HFn : std_logic;
75 signal S_EFn : std_logic;
76 signal S_FFn : std_logic;
77 signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);
78 signal S_HFn : std_logic;
79 signal R_FIFO_D_IN : std_logic_vector (7 downto 0);
80 signal R_FIFO_READn : std_logic;
81 signal R_FIFO_RESETn : std_logic;
82 signal R_FIFO_RTn : std_logic;
83 signal R_FIFO_WRITEn : std_logic;
84 signal S_FIFO_D_IN : std_logic_vector (7 downto 0);
85 signal S_FIFO_READn : std_logic;
86 signal S_FIFO_RESETn : std_logic;
87 signal S_FIFO_RTn : std_logic;
88 signal S_FIFO_WRITEn : std_logic;
89 signal SERIAL_IN : std_logic;
90 signal SPC_RDY_IN : std_logic;
91 signal SERIAL_OUT : std_logic;
92 signal SPC_RDY_OUT : std_logic;
93 signal watch : std_logic;
94 signal control0 : std_logic_vector(35 downto 0);
95 signal data : std_logic_vector(63 downto 0);
96 signal trig0 : std_logic_vector(7 downto 0);
97
98 component MESS_1_TB
99 Port ( DEVSELn : In std_logic;
100 INTAn : In std_logic;
101 KONST_1 : In std_logic;
102 PCI_IDSEL : In std_logic;
103 REG_OUT_XX7 : In std_logic_vector (7 downto 0);
104 TB_DEVSELn : Out std_logic;
105 TB_INTAn : Out std_logic;
106 TB_PCI_IDSEL : Out std_logic );
107 end component;
108
109 component VEN_REV_ID
110 Port ( REV_ID : Out std_logic_vector (7 downto 0);
111 VEN_ID : Out std_logic_vector (15 downto 0) );
112 end component;
113
114 component INTERRUPT
115 Port ( INT_IN_0 : In std_logic;
116 INT_IN_1 : In std_logic;
117 INT_IN_2 : In std_logic;
118 INT_IN_3 : In std_logic;
119 INT_IN_4 : In std_logic;
120 INT_IN_5 : In std_logic;
121 INT_IN_6 : In std_logic;
122 INT_IN_7 : In std_logic;
123 INT_MASKE : In std_logic_vector (7 downto 0);
124 INT_RES : In std_logic_vector (7 downto 0);
125 PCI_CLOCK : In std_logic;
126 PCI_RSTn : In std_logic;
127 READ_XX5_4 : In std_logic;
128 RESET : In std_logic;
129 TAST_RESn : In std_logic;
130 TAST_SETn : In std_logic;
131 TRDYn : In std_logic;
132 INT_REG : Out std_logic_vector (7 downto 0);
133 INTAn : Out std_logic;
134 PCI_INTAn : Out std_logic );
135 end component;
136
137 component FIFO_CONTROL
138 Port ( FIFO_RDn : In std_logic;
139 FLAG_IN_0 : In std_logic;
140 FLAG_IN_4 : In std_logic;
141 HOLD : In std_logic;
142 KONST_1 : In std_logic;
143 PCI_CLOCK : In std_logic;
144 PSC_ENABLE : In std_logic;
145 R_EFn : In std_logic;
146 R_FFn : In std_logic;
147 R_HFn : In std_logic;
148 RESET : In std_logic;
149 S_EFn : In std_logic;
150 S_FFn : In std_logic;
151 S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
152 S_HFn : In std_logic;
153 SERIAL_IN : In std_logic;
154 SPC_ENABLE : In std_logic;
155 SPC_RDY_IN : In std_logic;
156 WRITE_XX1_0 : In std_logic;
157 R_ERROR : Out std_logic;
158 R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
159 R_FIFO_READn : Out std_logic;
160 R_FIFO_RESETn : Out std_logic;
161 R_FIFO_RETRANSMITn : Out std_logic;
162 R_FIFO_WRITEn : Out std_logic;
163 RESERVE : Out std_logic;
164 S_ERROR : Out std_logic;
165 S_FIFO_READn : Out std_logic;
166 S_FIFO_RESETn : Out std_logic;
167 S_FIFO_RETRANSMITn : Out std_logic;
168 S_FIFO_WRITEn : Out std_logic;
169 SERIAL_OUT : Out std_logic;
170 SPC_RDY_OUT : Out std_logic;
171 SR_ERROR : Out std_logic;
172 SYNC_FLAG : Out std_logic_vector (7 downto 0) );
173 end component;
174
175 component PCI_TOP
176 Port ( FLAG : In std_logic_vector (7 downto 0);
177 INT_REG : In std_logic_vector (7 downto 0);
178 PCI_CBEn : In std_logic_vector (3 downto 0);
179 PCI_CLOCK : In std_logic;
180 PCI_FRAMEn : In std_logic;
181 PCI_IDSEL : In std_logic;
182 PCI_IRDYn : In std_logic;
183 PCI_RSTn : In std_logic;
184 R_FIFO_Q : In std_logic_vector (7 downto 0);
185 REVISON_ID : In std_logic_vector (7 downto 0);
186 VENDOR_ID : In std_logic_vector (15 downto 0);
187 PCI_AD : InOut std_logic_vector (31 downto 0);
188 PCI_PAR : InOut std_logic;
189 AD_REG : Out std_logic_vector (31 downto 0);
190 DEVSELn : Out std_logic;
191 FIFO_RDn : Out std_logic;
192 PCI_DEVSELn : Out std_logic;
193 PCI_PERRn : Out std_logic;
194 PCI_SERRn : Out std_logic;
195 PCI_STOPn : Out std_logic;
196 PCI_TRDYn : Out std_logic;
197 READ_SEL : Out std_logic_vector (1 downto 0);
198 READ_XX1_0 : Out std_logic;
199 READ_XX3_2 : Out std_logic;
200 READ_XX5_4 : Out std_logic;
201 READ_XX7_6 : Out std_logic;
202 REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
203 REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
204 REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
205 TRDYn : Out std_logic;
206 WRITE_XX1_0 : Out std_logic;
207 WRITE_XX3_2 : Out std_logic;
208 WRITE_XX5_4 : Out std_logic;
209 WRITE_XX7_6 : Out std_logic );
210 end component;
211
212 component fifo_generator_v3_2
213 port (
214 clk: IN std_logic;
215 din: IN std_logic_VECTOR(7 downto 0);
216 rd_en: IN std_logic;
217 rst: IN std_logic;
218 wr_en: IN std_logic;
219 almost_empty: OUT std_logic;
220 almost_full: OUT std_logic;
221 dout: OUT std_logic_VECTOR(7 downto 0);
222 empty: OUT std_logic;
223 full: OUT std_logic;
224 prog_full: OUT std_logic);
225 end component;
226
227 component icon
228 port
229 (
230 control0 : out std_logic_vector(35 downto 0)
231 );
232 end component;
233
234 component ila
235 port
236 (
237 control : in std_logic_vector(35 downto 0);
238 clk : in std_logic;
239 data : in std_logic_vector(63 downto 0);
240 trig0 : in std_logic_vector(7 downto 0)
241 );
242 end component;
243
244
245 begin
246 SERIAL_IN <= SERIAL_OUT;
247 SPC_RDY_IN <= SPC_RDY_OUT;
248 LED_2 <= TAST_RESn;
249 LED_3 <= TAST_SETn;
250 LED_4 <= '0';
251 LED_5 <= not watch;
252 PCI_INTAn <= watch;
253 trig0(7 downto 0) <= (others => '0');
254 data(31 downto 0) <= PCI_AD(31 downto 0);
255 data(32) <= watch;
256
257 data(33) <= R_EFn;
258 data(34) <= R_HFn;
259 data(35) <= R_FFn;
260 data(36) <= R_FIFO_READn;
261 data(37) <= R_FIFO_RESETn;
262 data(38) <= R_FIFO_RTn;
263 data(39) <= R_FIFO_WRITEn;
264 data(40) <= S_EFn;
265 data(41) <= S_HFn;
266 data(42) <= S_FFn;
267 data(43) <= S_FIFO_READn;
268 data(44) <= S_FIFO_RESETn;
269 data(45) <= S_FIFO_RTn;
270 data(46) <= S_FIFO_WRITEn;
271 data(47) <= SERIAL_IN;
272 data(48) <= SPC_RDY_IN;
273 data(49) <= SERIAL_OUT;
274 data(50) <= SPC_RDY_OUT;
275
276 I19 : MESS_1_TB
277 Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
278 PCI_IDSEL=>PCI_IDSEL,
279 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
280 TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,
281 TB_PCI_IDSEL=>TB_IDSEL );
282 I18 : VEN_REV_ID
283 Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),
284 VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );
285 I16 : INTERRUPT
286 Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),
287 INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,
288 INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,
289 INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),
290 INT_RES(7 downto 0)=>AD_REG(7 downto 0),
291 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
292 READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),
293 TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,
294 TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),
295 INTAn=>INTAn, PCI_INTAn=>watch);
296 I14 : FIFO_CONTROL
297 Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,
298 FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,
299 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),
300 R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,
301 RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,
302 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
303 S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,
304 SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,
305 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
306 R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
307 R_FIFO_READn=>R_FIFO_READn,
308 R_FIFO_RESETn=>R_FIFO_RESETn,
309 R_FIFO_RETRANSMITn=>R_FIFO_RTn,
310 R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,
311 S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,
312 S_FIFO_RESETn=>S_FIFO_RESETn,
313 S_FIFO_RETRANSMITn=>S_FIFO_RTn,
314 S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,
315 SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,
316 SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );
317 I1 : PCI_TOP
318 Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),
319 INT_REG(7 downto 0)=>INT_REG(7 downto 0),
320 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
321 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
322 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
323 PCI_RSTn=>PCI_RSTn,
324 R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),
325 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
326 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
327 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
328 PCI_PAR=>PCI_PAR,
329 AD_REG(31 downto 0)=>AD_REG(31 downto 0),
330 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
331 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,
332 PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,
333 PCI_TRDYn=>PCI_TRDYn,
334 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
335 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
336 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,
337 REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),
338 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
339 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
340 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,
341 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
342 WRITE_XX7_6=>WRITE_XX7_6 );
343
344 receive_fifo : fifo_generator_v3_2
345 port map (
346 clk => PCI_CLOCK,
347 din => R_FIFO_D_IN,
348 rd_en => not R_FIFO_READn,
349 rst => not R_FIFO_RESETn,
350 wr_en => not R_FIFO_WRITEn,
351 dout => R_FIFO_Q_OUT,
352 empty => R_EFn,
353 full => R_FFn,
354 prog_full => R_HFn);
355
356 send_fifo : fifo_generator_v3_2
357 port map (
358 clk => PCI_CLOCK,
359 din => S_FIFO_D_IN,
360 rd_en => not S_FIFO_READn,
361 rst => not S_FIFO_RESETn,
362 wr_en => not S_FIFO_WRITEn,
363 dout => S_FIFO_Q_OUT,
364 empty => S_EFn,
365 full => S_FFn,
366 prog_full => S_HFn);
367
368 i_icon : icon
369 port map
370 (
371 control0 => control0
372 );
373
374 i_ila : ila
375 port map
376 (
377 control => control0,
378 clk => PCI_CLOCK,
379 data => data,
380 trig0 => trig0
381 );
382 end SCHEMATIC;
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