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[raggedstone] / dhwk / source / config_3Ch.vhd
1 -- J.STELZNER
2 -- INFORMATIK-3 LABOR
3 -- 23.08.2006
4 -- File: CONFIG_3CH.VHD
5
6 library IEEE;
7 use IEEE.std_logic_1164.all;
8
9 entity CONFIG_3CH is
10 port
11 (
12 PCI_CLOCK :in std_logic;
13 PCI_RSTn :in std_logic;
14 AD_REG :in std_logic_vector (31 downto 0);
15 CBE_REGn :in std_logic_vector ( 3 downto 0);
16 CONF_WR_3CH :in std_logic;
17 CONF_DATA_3CH :out std_logic_vector (31 downto 0)
18 );
19 end entity CONFIG_3CH;
20
21 architecture CONFIG_3CH_DESIGN of CONFIG_3CH is
22
23 -- PCI Configuration Space Header Addr : HEX 3C --
24
25 signal CONF_MAX_LAT :std_logic_vector (31 downto 24);
26 signal CONF_MIN_GNT :std_logic_vector (23 downto 16);
27 signal CONF_INT_PIN :std_logic_vector (15 downto 8);
28 signal CONF_INT_LINE :std_logic_vector ( 7 downto 0);
29
30 constant cmd_conf_write :std_logic_vector(3 downto 0) := "1011";
31
32 begin
33
34 --*******************************************************************
35 --*********** PCI Configuration Space Header "INTERRUPT" ************
36 --*******************************************************************
37
38 CONF_MAX_LAT <= X"00";
39 CONF_MIN_GNT <= X"00";
40 -- CONF_INT_PIN <= X"00"; -- Interrupt -
41 CONF_INT_PIN <= X"01"; -- Interrupt A
42 -- CONF_INT_PIN <= X"02"; -- Interrupt B
43 -- CONF_INT_PIN <= X"03"; -- Interrupt C
44 -- CONF_INT_PIN <= X"04"; -- Interrupt D
45 -- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert
46
47 process (PCI_CLOCK,PCI_RSTn)
48 begin
49 if PCI_RSTn = '0' then CONF_INT_LINE <= (others =>'0');
50
51 elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
52
53 if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then
54
55 CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
56 else CONF_INT_LINE(7 downto 0) <= CONF_INT_LINE(7 downto 0);
57 end if;
58
59 end if;
60
61 end process;
62
63 CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE ;
64
65 end architecture CONFIG_3CH_DESIGN;
66
67
68
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