working vio
[raggedstone] / dhwk / source / pci / top.vhd
1 -- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007
2
3 LIBRARY ieee;
4
5 USE ieee.std_logic_1164.ALL;
6 USE ieee.numeric_std.ALL;
7
8
9 entity dhwk is
10 Port ( KONST_1 : In std_logic;
11 PCI_CBEn : In std_logic_vector (3 downto 0);
12 PCI_CLOCK : In std_logic;
13 PCI_FRAMEn : In std_logic;
14 PCI_IDSEL : In std_logic;
15 PCI_IRDYn : In std_logic;
16 PCI_RSTn : In std_logic;
17 -- SERIAL_IN : In std_logic;
18 -- SPC_RDY_IN : In std_logic;
19 TAST_RESn : In std_logic;
20 TAST_SETn : In std_logic;
21 LED_2 : out std_logic;
22 LED_3 : out std_logic;
23 LED_4 : out std_logic;
24 LED_5 : out std_logic;
25 PCI_AD : InOut std_logic_vector (31 downto 0);
26 PCI_PAR : InOut std_logic;
27 PCI_DEVSELn : Out std_logic;
28 PCI_INTAn : Out std_logic;
29 PCI_PERRn : Out std_logic;
30 PCI_SERRn : Out std_logic;
31 PCI_STOPn : Out std_logic;
32 PCI_TRDYn : Out std_logic;
33 PCI_REQn : Out std_logic;
34 PCI_GNTn : In std_logic;
35 -- SERIAL_OUT : Out std_logic;
36 -- SPC_RDY_OUT : Out std_logic;
37 TB_IDSEL : Out std_logic;
38 TB_nDEVSEL : Out std_logic;
39 TB_nINTA : Out std_logic );
40 end dhwk;
41
42 architecture SCHEMATIC of dhwk is
43
44 SIGNAL gnd : std_logic := '0';
45 SIGNAL vcc : std_logic := '1';
46
47 signal READ_XX7_6 : std_logic;
48 signal RESERVE : std_logic;
49 signal SR_ERROR : std_logic;
50 signal R_ERROR : std_logic;
51 signal S_ERROR : std_logic;
52 signal WRITE_XX3_2 : std_logic;
53 signal WRITE_XX5_4 : std_logic;
54 signal WRITE_XX7_6 : std_logic;
55 signal READ_XX1_0 : std_logic;
56 signal READ_XX3_2 : std_logic;
57 signal INTAn : std_logic;
58 signal TRDYn : std_logic;
59 signal READ_XX5_4 : std_logic;
60 signal DEVSELn : std_logic;
61 signal FIFO_RDn : std_logic;
62 signal WRITE_XX1_0 : std_logic;
63 signal REG_OUT_XX6 : std_logic_vector (7 downto 0);
64 signal SYNC_FLAG : std_logic_vector (7 downto 0);
65 signal INT_REG : std_logic_vector (7 downto 0);
66 signal REVISON_ID : std_logic_vector (7 downto 0);
67 signal VENDOR_ID : std_logic_vector (15 downto 0);
68 signal READ_SEL : std_logic_vector (1 downto 0);
69 signal AD_REG : std_logic_vector (31 downto 0);
70 signal REG_OUT_XX7 : std_logic_vector (7 downto 0);
71 signal R_EFn : std_logic;
72 signal R_FFn : std_logic;
73 signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);
74 signal R_HFn : std_logic;
75 signal S_EFn : std_logic;
76 signal S_FFn : std_logic;
77 signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);
78 signal S_HFn : std_logic;
79 signal R_FIFO_D_IN : std_logic_vector (7 downto 0);
80 signal R_FIFO_READn : std_logic;
81 signal R_FIFO_RESETn : std_logic;
82 signal R_FIFO_RTn : std_logic;
83 signal R_FIFO_WRITEn : std_logic;
84 signal S_FIFO_D_IN : std_logic_vector (7 downto 0);
85 signal S_FIFO_READn : std_logic;
86 signal S_FIFO_RESETn : std_logic;
87 signal S_FIFO_RTn : std_logic;
88 signal S_FIFO_WRITEn : std_logic;
89 signal SERIAL_IN : std_logic;
90 signal SPC_RDY_IN : std_logic;
91 signal SERIAL_OUT : std_logic;
92 signal SPC_RDY_OUT : std_logic;
93 signal led_PCI_INTA : std_logic;
94 signal watch_PCI_INTAn : std_logic;
95 signal watch_PCI_TRDYn : std_logic;
96 signal watch_PCI_STOPn : std_logic;
97 signal watch_PCI_SERRn : std_logic;
98 signal watch_PCI_PERRn : std_logic;
99 signal watch_PCI_REQn : std_logic;
100 signal control0 : std_logic_vector(35 downto 0);
101 signal control1 : std_logic_vector(35 downto 0);
102 signal data : std_logic_vector(95 downto 0);
103 signal trig0 : std_logic_vector(31 downto 0);
104 signal vio_sync_out : std_logic_vector(0 downto 0);
105 signal vio_async_in : std_logic_vector(3 downto 0);
106
107 component MESS_1_TB
108 Port ( DEVSELn : In std_logic;
109 INTAn : In std_logic;
110 KONST_1 : In std_logic;
111 PCI_IDSEL : In std_logic;
112 REG_OUT_XX7 : In std_logic_vector (7 downto 0);
113 TB_DEVSELn : Out std_logic;
114 TB_INTAn : Out std_logic;
115 TB_PCI_IDSEL : Out std_logic );
116 end component;
117
118 component VEN_REV_ID
119 Port ( REV_ID : Out std_logic_vector (7 downto 0);
120 VEN_ID : Out std_logic_vector (15 downto 0) );
121 end component;
122
123 component INTERRUPT
124 Port ( INT_IN_0 : In std_logic;
125 INT_IN_1 : In std_logic;
126 INT_IN_2 : In std_logic;
127 INT_IN_3 : In std_logic;
128 INT_IN_4 : In std_logic;
129 INT_IN_5 : In std_logic;
130 INT_IN_6 : In std_logic;
131 INT_IN_7 : In std_logic;
132 INT_MASKE : In std_logic_vector (7 downto 0);
133 INT_RES : In std_logic_vector (7 downto 0);
134 PCI_CLOCK : In std_logic;
135 PCI_RSTn : In std_logic;
136 READ_XX5_4 : In std_logic;
137 RESET : In std_logic;
138 TAST_RESn : In std_logic;
139 TAST_SETn : In std_logic;
140 TRDYn : In std_logic;
141 INT_REG : Out std_logic_vector (7 downto 0);
142 INTAn : Out std_logic;
143 PCI_INTAn : Out std_logic );
144 end component;
145
146 component FIFO_CONTROL
147 Port ( FIFO_RDn : In std_logic;
148 FLAG_IN_0 : In std_logic;
149 FLAG_IN_4 : In std_logic;
150 HOLD : In std_logic;
151 KONST_1 : In std_logic;
152 PCI_CLOCK : In std_logic;
153 PSC_ENABLE : In std_logic;
154 R_EFn : In std_logic;
155 R_FFn : In std_logic;
156 R_HFn : In std_logic;
157 RESET : In std_logic;
158 S_EFn : In std_logic;
159 S_FFn : In std_logic;
160 S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
161 S_HFn : In std_logic;
162 SERIAL_IN : In std_logic;
163 SPC_ENABLE : In std_logic;
164 SPC_RDY_IN : In std_logic;
165 WRITE_XX1_0 : In std_logic;
166 R_ERROR : Out std_logic;
167 R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
168 R_FIFO_READn : Out std_logic;
169 R_FIFO_RESETn : Out std_logic;
170 R_FIFO_RETRANSMITn : Out std_logic;
171 R_FIFO_WRITEn : Out std_logic;
172 RESERVE : Out std_logic;
173 S_ERROR : Out std_logic;
174 S_FIFO_READn : Out std_logic;
175 S_FIFO_RESETn : Out std_logic;
176 S_FIFO_RETRANSMITn : Out std_logic;
177 S_FIFO_WRITEn : Out std_logic;
178 SERIAL_OUT : Out std_logic;
179 SPC_RDY_OUT : Out std_logic;
180 SR_ERROR : Out std_logic;
181 SYNC_FLAG : Out std_logic_vector (7 downto 0) );
182 end component;
183
184 component PCI_TOP
185 Port ( FLAG : In std_logic_vector (7 downto 0);
186 INT_REG : In std_logic_vector (7 downto 0);
187 PCI_CBEn : In std_logic_vector (3 downto 0);
188 PCI_CLOCK : In std_logic;
189 PCI_FRAMEn : In std_logic;
190 PCI_IDSEL : In std_logic;
191 PCI_IRDYn : In std_logic;
192 PCI_RSTn : In std_logic;
193 R_FIFO_Q : In std_logic_vector (7 downto 0);
194 REVISON_ID : In std_logic_vector (7 downto 0);
195 VENDOR_ID : In std_logic_vector (15 downto 0);
196 PCI_AD : InOut std_logic_vector (31 downto 0);
197 PCI_PAR : InOut std_logic;
198 AD_REG : Out std_logic_vector (31 downto 0);
199 DEVSELn : Out std_logic;
200 FIFO_RDn : Out std_logic;
201 PCI_DEVSELn : Out std_logic;
202 PCI_PERRn : Out std_logic;
203 PCI_SERRn : Out std_logic;
204 PCI_STOPn : Out std_logic;
205 PCI_TRDYn : Out std_logic;
206 READ_SEL : Out std_logic_vector (1 downto 0);
207 READ_XX1_0 : Out std_logic;
208 READ_XX3_2 : Out std_logic;
209 READ_XX5_4 : Out std_logic;
210 READ_XX7_6 : Out std_logic;
211 REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
212 REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
213 REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
214 TRDYn : Out std_logic;
215 WRITE_XX1_0 : Out std_logic;
216 WRITE_XX3_2 : Out std_logic;
217 WRITE_XX5_4 : Out std_logic;
218 WRITE_XX7_6 : Out std_logic );
219 end component;
220
221 component dhwk_fifo
222 port (
223 clk: IN std_logic;
224 din: IN std_logic_VECTOR(7 downto 0);
225 rd_en: IN std_logic;
226 rst: IN std_logic;
227 wr_en: IN std_logic;
228 almost_empty: OUT std_logic;
229 almost_full: OUT std_logic;
230 dout: OUT std_logic_VECTOR(7 downto 0);
231 empty: OUT std_logic;
232 full: OUT std_logic;
233 prog_full: OUT std_logic);
234 end component;
235
236 component icon
237 port
238 (
239 control0 : out std_logic_vector(35 downto 0);
240 control1 : out std_logic_vector(35 downto 0)
241 );
242 end component;
243
244 component ila
245 port
246 (
247 control : in std_logic_vector(35 downto 0);
248 clk : in std_logic;
249 data : in std_logic_vector(95 downto 0);
250 trig0 : in std_logic_vector(31 downto 0)
251 );
252 end component;
253
254 component vio
255 port
256 (
257 control : in std_logic_vector(35 downto 0);
258 clk : in std_logic;
259 async_in : in std_logic_vector(3 downto 0);
260 sync_out : out std_logic_vector(0 downto 0)
261 );
262 end component;
263
264
265 begin
266 process(PCI_CLOCK)
267 begin
268 if rising_edge(PCI_CLOCK) then
269 led_PCI_INTA <= not (watch_PCI_INTAn and (not vio_sync_out(0)));
270 end if;
271 end process;
272
273 watch_PCI_REQn <= '1';
274 SERIAL_IN <= SERIAL_OUT;
275 SPC_RDY_IN <= SPC_RDY_OUT;
276 LED_2 <= not PCI_RSTn;
277 LED_3 <= not PCI_IDSEL;
278 LED_4 <= not PCI_FRAMEn;
279 LED_5 <= led_PCI_INTA;
280 PCI_INTAn <= (watch_PCI_INTAn and (not vio_sync_out(0)));
281
282 vio_async_in(3 downto 0) <= (
283 0 => not PCI_RSTn,
284 1 => not PCI_IDSEL,
285 2 => not PCI_FRAMEn,
286 3 => led_PCI_INTA
287 );
288
289 trig0(31 downto 0) <= (
290 0 => watch_PCI_INTAn,
291 1 => R_FIFO_READn,
292 2 => R_FIFO_WRITEn,
293 3 => S_FIFO_READn,
294 4 => S_FIFO_WRITEn,
295 5 => PCI_RSTn,
296 6 => PCI_IDSEL,
297 16 => PCI_AD(0),
298 17 => PCI_AD(1),
299 18 => PCI_AD(2),
300 19 => PCI_AD(3),
301 20 => PCI_AD(4),
302 21 => PCI_AD(5),
303 22 => PCI_AD(6),
304 23 => PCI_AD(7),
305 27 => PCI_FRAMEn,
306 28 => PCI_CBEn(0),
307 29 => PCI_CBEn(1),
308 30 => PCI_CBEn(2),
309 31 => PCI_CBEn(3),
310 others => '0');
311
312 data(0) <= watch_PCI_INTAn;
313 data(1) <= R_EFn;
314 data(2) <= R_HFn;
315 data(3) <= R_FFn;
316 data(4) <= R_FIFO_READn;
317 data(5) <= R_FIFO_RESETn;
318 data(6) <= R_FIFO_RTn;
319 data(7) <= R_FIFO_WRITEn;
320 data(8) <= S_EFn;
321 data(9) <= S_HFn;
322 data(10) <= S_FFn;
323 data(11) <= S_FIFO_READn;
324 data(12) <= S_FIFO_RESETn;
325 data(13) <= S_FIFO_RTn;
326 data(14) <= S_FIFO_WRITEn;
327 data(15) <= SERIAL_IN;
328 data(16) <= SPC_RDY_IN;
329 data(17) <= SERIAL_OUT;
330 data(18) <= SPC_RDY_OUT;
331 data(26 downto 19) <= S_FIFO_Q_OUT;
332 data(34 downto 27) <= R_FIFO_Q_OUT;
333 data(66 downto 35) <= PCI_AD(31 downto 0);
334 data(70 downto 67) <= PCI_CBEn(3 downto 0);
335 data(71) <= PCI_FRAMEn;
336 data(72) <= PCI_IDSEL;
337 PCI_TRDYn <= watch_PCI_TRDYn;
338 data(73) <= watch_PCI_TRDYn;
339 data(74) <= PCI_IRDYn;
340 PCI_STOPn <= watch_PCI_STOPn;
341 data(75) <= watch_PCI_STOPn;
342 PCI_SERRn <= watch_PCI_SERRn;
343 data(76) <= watch_PCI_SERRn;
344 PCI_PERRn <= watch_PCI_PERRn;
345 data(77) <= watch_PCI_PERRn;
346 PCI_REQn <= watch_PCI_REQn;
347 data(78) <= watch_PCI_REQn;
348 data(79) <= PCI_GNTn;
349
350 I19 : MESS_1_TB
351 Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
352 PCI_IDSEL=>PCI_IDSEL,
353 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
354 TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,
355 TB_PCI_IDSEL=>TB_IDSEL );
356 I18 : VEN_REV_ID
357 Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),
358 VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );
359 I16 : INTERRUPT
360 Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),
361 INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,
362 INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,
363 INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),
364 INT_RES(7 downto 0)=>AD_REG(7 downto 0),
365 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
366 READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),
367 TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,
368 TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),
369 INTAn=>INTAn, PCI_INTAn=>watch_PCI_INTAn);
370 I14 : FIFO_CONTROL
371 Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,
372 FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,
373 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),
374 R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,
375 RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,
376 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
377 S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,
378 SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,
379 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
380 R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
381 R_FIFO_READn=>R_FIFO_READn,
382 R_FIFO_RESETn=>R_FIFO_RESETn,
383 R_FIFO_RETRANSMITn=>R_FIFO_RTn,
384 R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,
385 S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,
386 S_FIFO_RESETn=>S_FIFO_RESETn,
387 S_FIFO_RETRANSMITn=>S_FIFO_RTn,
388 S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,
389 SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,
390 SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );
391 I1 : PCI_TOP
392 Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),
393 INT_REG(7 downto 0)=>INT_REG(7 downto 0),
394 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
395 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
396 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
397 PCI_RSTn=>PCI_RSTn,
398 R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),
399 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
400 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
401 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
402 PCI_PAR=>PCI_PAR,
403 AD_REG(31 downto 0)=>AD_REG(31 downto 0),
404 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
405 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>watch_PCI_PERRn,
406 PCI_SERRn=>watch_PCI_SERRn, PCI_STOPn=>watch_PCI_STOPn,
407 PCI_TRDYn=>watch_PCI_TRDYn,
408 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
409 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
410 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,
411 REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),
412 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
413 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
414 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,
415 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
416 WRITE_XX7_6=>WRITE_XX7_6 );
417
418 receive_fifo : dhwk_fifo
419 port map (
420 clk => PCI_CLOCK,
421 din => R_FIFO_D_IN,
422 rd_en => not R_FIFO_READn,
423 rst => not R_FIFO_RESETn,
424 wr_en => not R_FIFO_WRITEn,
425 dout => R_FIFO_Q_OUT,
426 empty => R_EFn,
427 full => R_FFn,
428 prog_full => R_HFn);
429
430 send_fifo : dhwk_fifo
431 port map (
432 clk => PCI_CLOCK,
433 din => S_FIFO_D_IN,
434 rd_en => not S_FIFO_READn,
435 rst => not S_FIFO_RESETn,
436 wr_en => not S_FIFO_WRITEn,
437 dout => S_FIFO_Q_OUT,
438 empty => S_EFn,
439 full => S_FFn,
440 prog_full => S_HFn);
441
442 i_icon : icon
443 port map
444 (
445 control0 => control0,
446 control1 => control1
447 );
448
449 i_ila : ila
450 port map
451 (
452 control => control0,
453 clk => PCI_CLOCK,
454 data => data,
455 trig0 => trig0
456 );
457
458 i_vio : vio
459 port map
460 (
461 control => control1,
462 clk => PCI_CLOCK,
463 async_in => vio_async_in,
464 sync_out => vio_sync_out
465 );
466 end SCHEMATIC;
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