Update to EDK 9.2
[raggedstone] / xps / raggedstone.mhs
1
2 # ##############################################################################
3 # Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4
4 # Thu Mar 22 21:42:23 2007
5 # Target Board: Custom
6 # Family: spartan3
7 # Device: xc3s1500
8 # Package: fg456
9 # Speed Grade: -4
10 # Processor: Microblaze
11 # System clock frequency: 50.000000 MHz
12 # Debug interface: On-Chip HW Debug Module
13 # On Chip Memory : 64 KB
14 # ##############################################################################
15 PARAMETER VERSION = 2.1.0
16
17
18 PORT fpga_0_RS232_req_to_send_pin = net_gnd, DIR = O
19 PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I
20 PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O
21 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
22 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
23 PORT RS232foff = net_vcc, DIR = O
24 PORT MEM_FLASH_DQ = FLASH_DQ, DIR = IO, VEC = [7:0]
25 PORT MEM_FLASH_ADDR = FLASH_ADDR, DIR = O, VEC = [18:0]
26 PORT MEM_FLASH_CE = FLASH_CEN, DIR = O, VEC = [0:0]
27 PORT MEM_FLASH_OE = FLASH_OEN, DIR = O, VEC = [0:0]
28 PORT MEM_FLASH_WE = FLASH_WEN, DIR = O
29 PORT SEVENSEG_out = GPIO_7SEG_OUT, DIR = O, VEC = [0:12]
30 PORT DBG_FLASH_ADDR = FLASH_ADDR_split, DIR = O, VEC = [0:31]
31 PORT LED_out = LEDS_GPIO_d_out, DIR = O, VEC = [0:3]
32
33
34 BEGIN lmb_v10
35 PARAMETER INSTANCE = ilmb
36 PARAMETER HW_VER = 1.00.a
37 PORT SYS_Rst = sys_bus_reset
38 PORT LMB_Clk = sys_clk_s
39 END
40
41 BEGIN lmb_v10
42 PARAMETER INSTANCE = dlmb
43 PARAMETER HW_VER = 1.00.a
44 PORT SYS_Rst = sys_bus_reset
45 PORT LMB_Clk = sys_clk_s
46 END
47
48 BEGIN bram_block
49 PARAMETER INSTANCE = lmb_bram
50 PARAMETER HW_VER = 1.00.a
51 BUS_INTERFACE PORTA = dlmb_cntlr_BRAM_PORT
52 BUS_INTERFACE PORTB = ilmb_cntlr_BRAM_PORT
53 END
54
55 BEGIN chipscope_icon
56 PARAMETER INSTANCE = chipscope_icon_0
57 PARAMETER HW_VER = 1.01.a
58 PORT control0 = ila_control0
59 END
60
61 BEGIN chipscope_ila
62 PARAMETER INSTANCE = chipscope_ila_0
63 PARAMETER HW_VER = 1.01.a
64 PARAMETER C_NUM_DATA_SAMPLES = 1024
65 PARAMETER C_TRIG0_TRIGGER_IN_WIDTH = 19
66 PARAMETER C_TRIG1_UNITS = 0
67 PARAMETER C_TRIG2_UNITS = 0
68 PARAMETER C_TRIG0_UNITS = 1
69 PORT CHIPSCOPE_ILA_CONTROL = ila_control0
70 PORT CLK = sys_clk_s
71 PORT TRIG0 = FLASH_ADDR
72 END
73
74 BEGIN util_bus_split
75 PARAMETER INSTANCE = flash_split
76 PARAMETER HW_VER = 1.00.a
77 PARAMETER C_SIZE_IN = 32
78 PARAMETER C_SPLIT = 13
79 PORT Sig = FLASH_ADDR_split
80 PORT Out2 = FLASH_ADDR
81 END
82
83 BEGIN microblaze
84 PARAMETER INSTANCE = microblaze_0
85 PARAMETER HW_VER = 7.00.a
86 PARAMETER C_DEBUG_ENABLED = 1
87 PARAMETER C_NUMBER_OF_PC_BRK = 2
88 PARAMETER C_FAMILY = spartan3
89 PARAMETER C_INSTANCE = microblaze_0
90 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 0
91 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 0
92 BUS_INTERFACE DEBUG = mdm_0_MBDEBUG_0
93 BUS_INTERFACE IPLB = mb_plb
94 BUS_INTERFACE DPLB = mb_plb
95 BUS_INTERFACE DLMB = dlmb
96 BUS_INTERFACE ILMB = ilmb
97 PORT MB_RESET = mb_reset
98 END
99
100 BEGIN lmb_bram_if_cntlr
101 PARAMETER INSTANCE = dlmb_cntlr
102 PARAMETER HW_VER = 2.10.a
103 PARAMETER C_BASEADDR = 0x00000000
104 PARAMETER C_HIGHADDR = 0x00007fff
105 BUS_INTERFACE SLMB = dlmb
106 BUS_INTERFACE BRAM_PORT = dlmb_cntlr_BRAM_PORT
107 END
108
109 BEGIN lmb_bram_if_cntlr
110 PARAMETER INSTANCE = ilmb_cntlr
111 PARAMETER HW_VER = 2.10.a
112 PARAMETER C_BASEADDR = 0x00000000
113 PARAMETER C_HIGHADDR = 0x00007fff
114 BUS_INTERFACE SLMB = ilmb
115 BUS_INTERFACE BRAM_PORT = ilmb_cntlr_BRAM_PORT
116 END
117
118 BEGIN mdm
119 PARAMETER INSTANCE = debug_module
120 PARAMETER HW_VER = 1.00.a
121 PARAMETER C_BASEADDR = 0x84400000
122 PARAMETER C_HIGHADDR = 0x8440ffff
123 PARAMETER C_MB_DBG_PORTS = 1
124 BUS_INTERFACE MBDEBUG_0 = mdm_0_MBDEBUG_0
125 BUS_INTERFACE SPLB = mb_plb
126 PORT Debug_SYS_Rst = MB_Debug_Sys_Rst
127 END
128
129 BEGIN plb_v46
130 PARAMETER INSTANCE = mb_plb
131 PARAMETER HW_VER = 1.00.a
132 PORT SYS_Rst = sys_bus_reset
133 PORT PLB_Clk = sys_clk_s
134 END
135
136 BEGIN xps_gpio
137 PARAMETER INSTANCE = LEDS
138 PARAMETER HW_VER = 1.00.a
139 PARAMETER C_GPIO_WIDTH = 4
140 PARAMETER C_BASEADDR = 0x84418000
141 PARAMETER C_HIGHADDR = 0x844181ff
142 BUS_INTERFACE SPLB = mb_plb
143 PORT GPIO_d_out = LEDS_GPIO_d_out
144 END
145
146 BEGIN xps_uartlite
147 PARAMETER INSTANCE = RS232
148 PARAMETER HW_VER = 1.00.a
149 PARAMETER C_BAUDRATE = 115200
150 PARAMETER C_USE_PARITY = 0
151 PARAMETER C_BASEADDR = 0x84000000
152 PARAMETER C_HIGHADDR = 0x8400ffff
153 PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000
154 BUS_INTERFACE SPLB = mb_plb
155 PORT TX = fpga_0_RS232_TX
156 PORT RX = fpga_0_RS232_RX
157 END
158
159 BEGIN proc_sys_reset
160 PARAMETER INSTANCE = proc_sys_reset_0
161 PARAMETER HW_VER = 2.00.a
162 PARAMETER C_EXT_RESET_HIGH = 0
163 PORT MB_Debug_Sys_Rst = MB_Debug_Sys_Rst
164 PORT Bus_Struct_Reset = sys_bus_reset
165 PORT MB_Reset = mb_reset
166 PORT Ext_Reset_In = sys_rst_s
167 PORT Slowest_sync_clk = sys_clk_s
168 PORT Dcm_locked = dcm_locked
169 END
170
171 BEGIN xps_mch_emc
172 PARAMETER INSTANCE = FLASH
173 PARAMETER HW_VER = 1.00.a
174 PARAMETER C_MEM0_BASEADDR = 0x20000000
175 PARAMETER C_MEM0_HIGHADDR = 0x2007FFFF
176 PARAMETER C_NUM_CHANNELS = 0
177 PARAMETER C_MAX_MEM_WIDTH = 8
178 PARAMETER C_MEM0_WIDTH = 8
179 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
180 PARAMETER C_TCEDV_PS_MEM_0 = 70000
181 PARAMETER C_TAVDV_PS_MEM_0 = 70000
182 PARAMETER C_THZCE_PS_MEM_0 = 25000
183 PARAMETER C_THZOE_PS_MEM_0 = 25000
184 PARAMETER C_TWC_PS_MEM_0 = 110000
185 PARAMETER C_TWP_PS_MEM_0 = 70000
186 PARAMETER C_TLZWE_PS_MEM_0 = 15000
187 BUS_INTERFACE SPLB = mb_plb
188 PORT Mem_DQ = FLASH_DQ
189 PORT Mem_WEN = FLASH_WEN
190 PORT Mem_OEN = FLASH_OEN
191 PORT Mem_CEN = FLASH_CEN
192 PORT Mem_A = FLASH_ADDR_split
193 END
194
195 BEGIN xps_gpio
196 PARAMETER INSTANCE = SEVENSEG
197 PARAMETER HW_VER = 1.00.a
198 PARAMETER C_BASEADDR = 0x40000000
199 PARAMETER C_HIGHADDR = 0x400001FF
200 PARAMETER C_GPIO_WIDTH = 13
201 BUS_INTERFACE SPLB = mb_plb
202 PORT GPIO_d_out = GPIO_7SEG_OUT
203 END
204
205 BEGIN clock_generator
206 PARAMETER INSTANCE = clock_generator_0
207 PARAMETER HW_VER = 1.00.a
208 PARAMETER C_CLKIN_FREQ = 50000000
209 PARAMETER C_EXT_RESET_HIGH = 1
210 PARAMETER C_CLKOUT0_FREQ = 50000000
211 PARAMETER C_CLKOUT0_PHASE = 0
212 PARAMETER C_CLKOUT0_GROUP = NONE
213 PORT CLKIN = dcm_clk_s
214 PORT CLKOUT0 = sys_clk_s
215 PORT RST = net_gnd
216 PORT LOCKED = dcm_locked
217 END
218
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