22c49f370cec22aa770ca6b8772bd08b9eabbc01
[raggedstone] / dhwk / fifo.xco
1 # BEGIN Project Options
2 SET addpads = False
3 SET asysymbol = False
4 SET busformat = BusFormatAngleBracketNotRipped
5 SET createndf = False
6 SET designentry = VHDL
7 SET device = xc3s1500
8 SET devicefamily = spartan3
9 SET flowvendor = Other
10 SET formalverification = False
11 SET foundationsym = False
12 SET implementationfiletype = Ngc
13 SET package = fg456
14 SET removerpms = False
15 SET simulationfiles = Behavioral
16 SET speedgrade = -4
17 SET verilogsim = False
18 SET vhdlsim = True
19 # END Project Options
20 # BEGIN Select
21 SELECT Fifo_Generator family Xilinx,_Inc. 3.2
22 # END Select
23 # BEGIN Parameters
24 CSET almost_empty_flag=true
25 CSET almost_full_flag=true
26 CSET component_name=fifo_generator_v3_2
27 CSET data_count=false
28 CSET data_count_width=12
29 CSET dout_reset_value=0
30 CSET empty_threshold_assert_value=2
31 CSET empty_threshold_negate_value=3
32 CSET fifo_implementation=Common_Clock_Block_RAM
33 CSET full_threshold_assert_value=2048
34 CSET full_threshold_negate_value=2047
35 CSET input_data_width=8
36 CSET input_depth=4096
37 CSET output_data_width=8
38 CSET output_depth=4096
39 CSET overflow_flag=false
40 CSET overflow_sense=Active_High
41 CSET performance_options=Standard_FIFO
42 CSET programmable_empty_type=No_Programmable_Empty_Threshold
43 CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
44 CSET read_clock_frequency=100
45 CSET read_data_count=false
46 CSET read_data_count_width=12
47 CSET reset_pin=true
48 CSET reset_type=Asynchronous_Reset
49 CSET underflow_flag=false
50 CSET underflow_sense=Active_High
51 CSET use_extra_logic=false
52 CSET valid_flag=false
53 CSET valid_sense=Active_High
54 CSET write_acknowledge_flag=false
55 CSET write_acknowledge_sense=Active_High
56 CSET write_clock_frequency=100
57 CSET write_data_count=false
58 CSET write_data_count_width=12
59 # END Parameters
60 GENERATE
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