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[raggedstone] / dhwk / source / Parity_4.vhd
1 -- J.STELZNER
2 -- INFORMATIK-3 LABOR
3 -- 23.08.2006
4 -- File: PARITY_4.VHD
5
6 library ieee;
7 use ieee.std_logic_1164.all;
8
9 entity PARITY_4 is
10 port
11 (
12 PAR_IN :in std_logic_vector(3 downto 0);
13 PAR_OUT :out std_logic
14 );
15 end entity PARITY_4;
16
17 architecture PARITY_4_DESIGN of PARITY_4 is
18
19 begin
20
21 PAR_OUT <= PAR_IN(3) xor PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0);
22
23 end architecture PARITY_4_DESIGN;
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