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[raggedstone] / dhwk / source / REG.vhd
1 -- J.STELZNER
2 -- INFORMATIK-3 LABOR
3 -- 23.08.2006
4 -- File: REG.VHD
5
6 library ieee;
7 use ieee.std_logic_1164.all;
8
9 entity REG is
10 port
11 (
12 CLOCK :in std_logic;
13 RESET :in std_logic;
14 WRITE :in std_logic;
15 REG_IN :in std_logic_vector(7 downto 0);
16 REG_OUT :out std_logic_vector(7 downto 0)
17 );
18 end entity REG;
19
20 architecture REG_DESIGN of REG is
21
22 signal SIG_REG :std_logic_vector (7 downto 0);
23
24 begin
25
26 process (CLOCK)
27 begin
28 if (CLOCK'event and CLOCK = '1') then
29 if RESET = '1' then
30 SIG_REG <= X"00";
31
32 elsif WRITE = '1' then
33 SIG_REG <= REG_IN;
34
35 else
36 SIG_REG <= SIG_REG;
37 end if;
38 end if;
39 end process;
40
41 REG_OUT <= SIG_REG;
42
43 end architecture REG_DESIGN;
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