git.zerfleddert.de Git - raggedstone/blob - ethernet/source/pci/pci_perr_en_crit.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  File name "perr_en_crit.v"                                  ////
   4 ////                                                              ////
   5 ////  This file is part of the "PCI bridge" project               ////
   6 ////  http://www.opencores.org/cores/pci/                         ////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Miha Dolenc (mihad@opencores.org)                     ////
  10 ////                                                              ////
  11 ////  All additional information is avaliable in the README       ////
  12 ////  file.                                                       ////
  13 ////                                                              ////
  14 ////                                                              ////
  15 //////////////////////////////////////////////////////////////////////
  16 ////                                                              ////
  17 //// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
  18 ////                                                              ////
  19 //// This source file may be used and distributed without         ////
  20 //// restriction provided that this copyright statement is not    ////
  21 //// removed from the file and that any derivative work contains  ////
  22 //// the original copyright notice and the associated disclaimer. ////
  23 ////                                                              ////
  24 //// This source file is free software; you can redistribute it   ////
  25 //// and/or modify it under the terms of the GNU Lesser General   ////
  26 //// Public License as published by the Free Software Foundation; ////
  27 //// either version 2.1 of the License, or (at your option) any   ////
  28 //// later version.                                               ////
  29 ////                                                              ////
  30 //// This source is distributed in the hope that it will be       ////
  31 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  32 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  33 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  34 //// details.                                                     ////
  35 ////                                                              ////
  36 //// You should have received a copy of the GNU Lesser General    ////
  37 //// Public License along with this source; if not, download it   ////
  38 //// from http://www.opencores.org/lgpl.shtml                     ////
  39 ////                                                              ////
  40 //////////////////////////////////////////////////////////////////////
  41 //
  42 // CVS Revision History
  43 //
  44 // $Log: pci_perr_en_crit.v,v $
  45 // Revision 1.1  2007-03-20 17:50:56  sithglan
  46 // add shit
  47 //
  48 // Revision 1.2  2003/02/13 18:26:33  mihad
  49 // Cleaned up the code. No functional changes.
  50 //
  51 // Revision 1.1  2003/01/27 16:49:31  mihad
  52 // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
  53 //
  54 // Revision 1.3  2002/02/01 15:25:13  mihad
  55 // Repaired a few bugs, updated specification, added test bench files and design document
  56 //
  57 // Revision 1.2  2001/10/05 08:14:30  mihad
  58 // Updated all files with inclusion of timescale file for simulation purposes.
  59 //
  60 // Revision 1.1.1.1  2001/10/02 15:33:47  mihad
  61 // New project directory structure
  62 //
  63 //
  64
  65 // module is used to separate logic which uses criticaly constrained inputs from slower logic.
  66 // It is used to synthesize critical timing logic separately with faster cells or without optimization
  67
  68 // This one is used in parity generator/checker for parity error (PERR#) output enable driving
  69
  70 // synopsys translate_off
  71 `include "timescale.v"
  72 // synopsys translate_on
  73
  74 module pci_perr_en_crit
  75 (
  76     reset_in,
  77     clk_in,
  78     perr_en_out,
  79     perr_en_reg_out,
  80     non_critical_par_in,
  81     pci_par_in,
  82     perr_generate_in,
  83     par_err_response_in
  84 ) ;
  85 output  perr_en_out,
  86         perr_en_reg_out ;
  87
  88 input   reset_in,
  89         clk_in,
  90         non_critical_par_in,
  91         pci_par_in,
  92         perr_generate_in,
  93         par_err_response_in ;
  94
  95 wire perr = par_err_response_in && perr_generate_in && ( non_critical_par_in ^ pci_par_in ) ;
  96
  97 // PERR# is enabled for two clocks after parity error is detected - one cycle active, another inactive
  98 reg perr_en_reg_out ;
  99 always@(posedge reset_in or posedge clk_in)
 100 begin
 101     if ( reset_in )
 102         perr_en_reg_out <= #1 1'b0 ;
 103     else
 104         perr_en_reg_out <= #1 perr ;
 105 end
 106
 107 assign perr_en_out = perr || perr_en_reg_out ;
 108
 109 endmodule