git.zerfleddert.de Git - raggedstone/blob - ethernet/source/pci/pci_wbs_wbb3_2_wbb2.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  File name "pci_wbs_wbb3_2_wbb2.v"                           ////
   4 ////                                                              ////
   5 ////  This file is part of the "PCI bridge" project               ////
   6 ////  http://www.opencores.org/cores/pci/                         ////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Miha Dolenc (mihad@opencores.org)                     ////
  10 ////                                                              ////
  11 ////                                                              ////
  12 ////                                                              ////
  13 //////////////////////////////////////////////////////////////////////
  14 ////                                                              ////
  15 //// Copyright (C) 2003 Miha Dolenc, mihad@opencores.org          ////
  16 ////                                                              ////
  17 //// This source file may be used and distributed without         ////
  18 //// restriction provided that this copyright statement is not    ////
  19 //// removed from the file and that any derivative work contains  ////
  20 //// the original copyright notice and the associated disclaimer. ////
  21 ////                                                              ////
  22 //// This source file is free software; you can redistribute it   ////
  23 //// and/or modify it under the terms of the GNU Lesser General   ////
  24 //// Public License as published by the Free Software Foundation; ////
  25 //// either version 2.1 of the License, or (at your option) any   ////
  26 //// later version.                                               ////
  27 ////                                                              ////
  28 //// This source is distributed in the hope that it will be       ////
  29 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  30 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  31 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  32 //// details.                                                     ////
  33 ////                                                              ////
  34 //// You should have received a copy of the GNU Lesser General    ////
  35 //// Public License along with this source; if not, download it   ////
  36 //// from http://www.opencores.org/lgpl.shtml                     ////
  37 ////                                                              ////
  38 //////////////////////////////////////////////////////////////////////
  39 //
  40 // CVS Revision History
  41 //
  42 // $Log: pci_wbs_wbb3_2_wbb2.v,v $
  43 // Revision 1.1  2007-03-20 17:50:56  sithglan
  44 // add shit
  45 //
  46 // Revision 1.5  2004/08/16 09:12:01  mihad
  47 // Removed unsinthesizable !== comparation.
  48 //
  49 // Revision 1.4  2004/01/24 11:54:18  mihad
  50 // Update! SPOCI Implemented!
  51 //
  52 // Revision 1.3  2003/12/19 11:11:30  mihad
  53 // Compact PCI Hot Swap support added.
  54 // New testcases added.
  55 // Specification updated.
  56 // Test application changed to support WB B3 cycles.
  57 //
  58 // Revision 1.2  2003/12/01 16:20:56  simons
  59 // ifdef - endif statements put in separate lines for flint compatibility.
  60 //
  61 // Revision 1.1  2003/08/12 13:58:19  mihad
  62 // Module that converts slave WISHBONE B3 accesses to
  63 // WISHBONE B2 accesses with CAB.
  64 //
  65 //
  66
  67 module pci_wbs_wbb3_2_wbb2
  68 (
  69     wb_clk_i,
  70     wb_rst_i,
  71
  72     wbs_cyc_i,
  73     wbs_cyc_o,
  74     wbs_stb_i,
  75     wbs_stb_o,
  76     wbs_adr_i,
  77     wbs_adr_o,
  78     wbs_dat_i_i,
  79     wbs_dat_i_o,
  80     wbs_dat_o_i,
  81     wbs_dat_o_o,
  82     wbs_we_i,
  83     wbs_we_o,
  84     wbs_sel_i,
  85     wbs_sel_o,
  86     wbs_ack_i,
  87     wbs_ack_o,
  88     wbs_err_i,
  89     wbs_err_o,
  90     wbs_rty_i,
  91     wbs_rty_o,
  92     wbs_cti_i,
  93     wbs_bte_i,
  94     wbs_cab_o,
  95     wb_init_complete_i
  96 ) ;
  97
  98 input       wb_clk_i    ;
  99 input       wb_rst_i    ;
 100
 101 input           wbs_cyc_i           ;
 102 output          wbs_cyc_o           ;
 103 input           wbs_stb_i           ;
 104 output          wbs_stb_o           ;
 105 input   [31:0]  wbs_adr_i           ;
 106 output  [31:0]  wbs_adr_o           ;
 107 input   [31:0]  wbs_dat_i_i         ;
 108 output  [31:0]  wbs_dat_i_o         ;
 109 input   [31:0]  wbs_dat_o_i         ;
 110 output  [31:0]  wbs_dat_o_o         ;
 111 input           wbs_we_i            ;
 112 output          wbs_we_o            ;
 113 input   [ 3:0]  wbs_sel_i           ;
 114 output  [ 3:0]  wbs_sel_o           ;
 115 input           wbs_ack_i           ;
 116 output          wbs_ack_o           ;
 117 input           wbs_err_i           ;
 118 output          wbs_err_o           ;
 119 input           wbs_rty_i           ;
 120 output          wbs_rty_o           ;
 121 input   [ 2:0]  wbs_cti_i           ;
 122 input   [ 1:0]  wbs_bte_i           ;
 123 output          wbs_cab_o           ;
 124 input           wb_init_complete_i  ;
 125
 126 reg             wbs_cyc_o           ;
 127 reg     [31:0]  wbs_adr_o           ;
 128 reg     [31:0]  wbs_dat_i_o         ;
 129 reg             wbs_dat_i_o_valid   ;
 130 reg     [31:0]  wbs_dat_o_o         ;
 131 reg             wbs_we_o            ;
 132 reg     [ 3:0]  wbs_sel_o           ;
 133 reg             wbs_ack_o           ;
 134 reg             wbs_err_o           ;
 135 reg             wbs_rty_o           ;
 136 reg             wbs_cab_o           ;
 137
 138 always@(posedge wb_rst_i or posedge wb_clk_i)
 139 begin
 140     if (wb_rst_i)
 141     begin
 142         wbs_cyc_o           <= 1'b0  ;
 143         wbs_adr_o           <= 32'h0 ;
 144         wbs_dat_i_o         <= 32'h0 ;
 145         wbs_dat_o_o         <= 32'h0 ;
 146         wbs_sel_o           <= 4'h0  ;
 147         wbs_we_o            <= 1'b0  ;
 148         wbs_dat_i_o_valid   <= 1'b0  ;
 149         wbs_cab_o           <= 1'b0  ;
 150     end
 151     else
 152     begin:transfer_and_transfer_adr_ctrl_blk
 153         reg start_cycle            ;
 154         reg [3:0] end_cycle        ;
 155         reg generate_int_adr       ;
 156
 157         start_cycle  = ~wbs_cyc_o & wbs_cyc_i & wbs_stb_i & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o & wb_init_complete_i ;
 158
 159         // there is a few conditions when cycle must be terminated
 160         // I've put them into bit array for better readability of the code
 161
 162         // 1st condition - pci bridge is signaling an error
 163         end_cycle[0] = wbs_err_i ;
 164
 165         // 2nd condition - pci bridge is signaling a retry - that can be ignored via the defines
 166         end_cycle[1] = wbs_rty_i
 167             `ifdef PCI_WBS_B3_RTY_DISABLE
 168                 & 1'b0
 169             `endif
 170                 ;
 171
 172         // 3rd condition - end non burst cycles as soon as pci bridge response is received
 173         end_cycle[2] = wbs_cyc_i & wbs_stb_i & wbs_ack_i & ~wbs_cab_o ;
 174
 175         // 4th condition - end cycle when acknowledge and strobe are both asserted and master is signaling end of burst
 176         end_cycle[3] = wbs_cyc_i & wbs_stb_i & wbs_ack_o & wbs_cab_o & (wbs_cti_i == 3'b111) ;
 177
 178         if (wbs_dat_i_o_valid)
 179         begin
 180             if (wbs_ack_i | wbs_err_i
 181                 `ifdef PCI_WBS_B3_RTY_DISABLE
 182                 `else
 183                     | wbs_rty_i
 184                 `endif
 185                     )
 186                 wbs_dat_i_o_valid <= 1'b0 ;
 187         end
 188         else
 189         begin
 190             if (wbs_cyc_i & wbs_stb_i & wbs_we_i & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o & wb_init_complete_i)
 191             begin
 192                 wbs_dat_i_o       <= wbs_dat_i_i ;
 193                 wbs_dat_i_o_valid <= 1'b1 ;
 194             end
 195         end
 196
 197         if (start_cycle)
 198         begin
 199             wbs_cyc_o   <= 1'b1         ;
 200             wbs_sel_o   <= wbs_sel_i    ;
 201             wbs_we_o    <= wbs_we_i     ;
 202
 203             if (wbs_cti_i == 3'b010)
 204             begin
 205                 case (wbs_bte_i)
 206                 2'b00:  begin
 207                             wbs_cab_o <= 1'b1 ;
 208                         end
 209                 2'b01:  begin
 210                             if (wbs_adr_i[3:2] == 2'b00)
 211                                 wbs_cab_o <= 1'b1 ;
 212                             else
 213                                 wbs_cab_o <= 1'b0 ;
 214                         end
 215                 2'b10:  begin
 216                             if (wbs_adr_i[4:2] == 3'b000)
 217                                 wbs_cab_o <= 1'b1 ;
 218                             else
 219                                 wbs_cab_o <= 1'b0 ;
 220                         end
 221                 2'b11:  begin
 222                             if (wbs_adr_i[5:2] == 4'b0000)
 223                                 wbs_cab_o <= 1'b1 ;
 224                             else
 225                                 wbs_cab_o <= 1'b0 ;
 226                         end
 227                 endcase
 228             end
 229             else
 230             begin
 231                 wbs_cab_o <= 1'b0 ;
 232             end
 233         end
 234         else if ( wbs_cyc_o & (|end_cycle) )
 235         begin
 236             wbs_cyc_o <= 1'b0 ;
 237         end
 238
 239         if (start_cycle)
 240             wbs_adr_o <= wbs_adr_i ;
 241         else if (wbs_ack_i)
 242             wbs_adr_o[31:2] <= wbs_adr_o[31:2] + 1'b1 ;
 243
 244         if (~wbs_we_o & wbs_ack_i)
 245             wbs_dat_o_o <= wbs_dat_o_i ;
 246     end
 247 end
 248
 249 always@(posedge wb_rst_i or posedge wb_clk_i)
 250 begin
 251     if (wb_rst_i)
 252     begin
 253         wbs_ack_o <= 1'b0 ;
 254         wbs_err_o <= 1'b0 ;
 255         wbs_rty_o <= 1'b0 ;
 256     end
 257     else
 258     begin
 259         if (wbs_ack_o)
 260             wbs_ack_o <= wbs_ack_i | ~wbs_stb_i ;
 261         else
 262             wbs_ack_o <= wbs_ack_i ;
 263
 264         if (wbs_err_o)
 265             wbs_err_o <= ~wbs_stb_i ;
 266         else
 267             wbs_err_o <= wbs_err_i ;
 268
 269     `ifdef PCI_WBS_B3_RTY_DISABLE
 270         wbs_rty_o <= 1'b0 ;
 271     `else
 272         if (wbs_rty_o)
 273             wbs_rty_o <= ~wbs_stb_i ;
 274         else
 275             wbs_rty_o <= wbs_rty_i ;
 276     `endif
 277     end
 278 end
 279
 280 assign wbs_stb_o = (wbs_cyc_o & ~wbs_we_o & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o) |
 281                    (wbs_cyc_o & wbs_stb_i & wbs_cab_o & ~wbs_we_o & wbs_cti_i != 3'b111) |
 282                    (wbs_cyc_o & wbs_we_o & wbs_dat_i_o_valid) ;
 283
 284 endmodule