2d25fcd56fbfd04c0d1db0c626379d5b2d7ba114
[raggedstone] / dhwk / source / top.vhd
1 -- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007
2
3
4
5 LIBRARY ieee;
6
7 USE ieee.std_logic_1164.ALL;
8 USE ieee.numeric_std.ALL;
9
10
11 entity dhwk is
12 Port ( KONST_1 : In std_logic;
13 PCI_CBEn : In std_logic_vector (3 downto 0);
14 PCI_CLOCK : In std_logic;
15 PCI_FRAMEn : In std_logic;
16 PCI_IDSEL : In std_logic;
17 PCI_IRDYn : In std_logic;
18 PCI_RSTn : In std_logic;
19 -- SERIAL_IN : In std_logic;
20 -- SPC_RDY_IN : In std_logic;
21 TAST_RESn : In std_logic;
22 TAST_SETn : In std_logic;
23 LED_2 : out std_logic;
24 LED_3 : out std_logic;
25 LED_4 : out std_logic;
26 LED_5 : out std_logic;
27 PCI_AD : InOut std_logic_vector (31 downto 0);
28 PCI_PAR : InOut std_logic;
29 PCI_DEVSELn : Out std_logic;
30 PCI_INTAn : Out std_logic;
31 PCI_PERRn : Out std_logic;
32 PCI_SERRn : Out std_logic;
33 PCI_STOPn : Out std_logic;
34 PCI_TRDYn : Out std_logic;
35 -- SERIAL_OUT : Out std_logic;
36 -- SPC_RDY_OUT : Out std_logic;
37 TB_IDSEL : Out std_logic;
38 TB_nDEVSEL : Out std_logic;
39 TB_nINTA : Out std_logic );
40 end dhwk;
41
42 architecture SCHEMATIC of dhwk is
43
44 SIGNAL gnd : std_logic := '0';
45 SIGNAL vcc : std_logic := '1';
46
47 signal READ_XX7_6 : std_logic;
48 signal RESERVE : std_logic;
49 signal SR_ERROR : std_logic;
50 signal R_ERROR : std_logic;
51 signal S_ERROR : std_logic;
52 signal WRITE_XX3_2 : std_logic;
53 signal WRITE_XX5_4 : std_logic;
54 signal WRITE_XX7_6 : std_logic;
55 signal READ_XX1_0 : std_logic;
56 signal READ_XX3_2 : std_logic;
57 signal INTAn : std_logic;
58 signal TRDYn : std_logic;
59 signal READ_XX5_4 : std_logic;
60 signal DEVSELn : std_logic;
61 signal FIFO_RDn : std_logic;
62 signal WRITE_XX1_0 : std_logic;
63 signal REG_OUT_XX6 : std_logic_vector (7 downto 0);
64 signal SYNC_FLAG : std_logic_vector (7 downto 0);
65 signal INT_REG : std_logic_vector (7 downto 0);
66 signal REVISON_ID : std_logic_vector (7 downto 0);
67 signal VENDOR_ID : std_logic_vector (15 downto 0);
68 signal READ_SEL : std_logic_vector (1 downto 0);
69 signal AD_REG : std_logic_vector (31 downto 0);
70 signal REG_OUT_XX7 : std_logic_vector (7 downto 0);
71 signal R_EFn : std_logic;
72 signal R_FFn : std_logic;
73 signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);
74 signal R_HFn : std_logic;
75 signal S_EFn : std_logic;
76 signal S_FFn : std_logic;
77 signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);
78 signal S_HFn : std_logic;
79 signal R_FIFO_D_IN : std_logic_vector (7 downto 0);
80 signal R_FIFO_READn : std_logic;
81 signal R_FIFO_RESETn : std_logic;
82 signal R_FIFO_RTn : std_logic;
83 signal R_FIFO_WRITEn : std_logic;
84 signal S_FIFO_D_IN : std_logic_vector (7 downto 0);
85 signal S_FIFO_READn : std_logic;
86 signal S_FIFO_RESETn : std_logic;
87 signal S_FIFO_RTn : std_logic;
88 signal S_FIFO_WRITEn : std_logic;
89 signal SERIAL_IN : std_logic;
90 signal SPC_RDY_IN : std_logic;
91 signal SERIAL_OUT : std_logic;
92 signal SPC_RDY_OUT : std_logic;
93 signal watch : std_logic;
94 signal control0 : std_logic_vector(35 downto 0);
95 signal data : std_logic_vector(35 downto 0);
96 signal trig0 : std_logic_vector(7 downto 0);
97
98 component MESS_1_TB
99 Port ( DEVSELn : In std_logic;
100 INTAn : In std_logic;
101 KONST_1 : In std_logic;
102 PCI_IDSEL : In std_logic;
103 REG_OUT_XX7 : In std_logic_vector (7 downto 0);
104 TB_DEVSELn : Out std_logic;
105 TB_INTAn : Out std_logic;
106 TB_PCI_IDSEL : Out std_logic );
107 end component;
108
109 component VEN_REV_ID
110 Port ( REV_ID : Out std_logic_vector (7 downto 0);
111 VEN_ID : Out std_logic_vector (15 downto 0) );
112 end component;
113
114 component INTERRUPT
115 Port ( INT_IN_0 : In std_logic;
116 INT_IN_1 : In std_logic;
117 INT_IN_2 : In std_logic;
118 INT_IN_3 : In std_logic;
119 INT_IN_4 : In std_logic;
120 INT_IN_5 : In std_logic;
121 INT_IN_6 : In std_logic;
122 INT_IN_7 : In std_logic;
123 INT_MASKE : In std_logic_vector (7 downto 0);
124 INT_RES : In std_logic_vector (7 downto 0);
125 PCI_CLOCK : In std_logic;
126 PCI_RSTn : In std_logic;
127 READ_XX5_4 : In std_logic;
128 RESET : In std_logic;
129 TAST_RESn : In std_logic;
130 TAST_SETn : In std_logic;
131 TRDYn : In std_logic;
132 INT_REG : Out std_logic_vector (7 downto 0);
133 INTAn : Out std_logic;
134 PCI_INTAn : Out std_logic );
135 end component;
136
137 component FIFO_CONTROL
138 Port ( FIFO_RDn : In std_logic;
139 FLAG_IN_0 : In std_logic;
140 FLAG_IN_4 : In std_logic;
141 HOLD : In std_logic;
142 KONST_1 : In std_logic;
143 PCI_CLOCK : In std_logic;
144 PSC_ENABLE : In std_logic;
145 R_EFn : In std_logic;
146 R_FFn : In std_logic;
147 R_HFn : In std_logic;
148 RESET : In std_logic;
149 S_EFn : In std_logic;
150 S_FFn : In std_logic;
151 S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
152 S_HFn : In std_logic;
153 SERIAL_IN : In std_logic;
154 SPC_ENABLE : In std_logic;
155 SPC_RDY_IN : In std_logic;
156 WRITE_XX1_0 : In std_logic;
157 R_ERROR : Out std_logic;
158 R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
159 R_FIFO_READn : Out std_logic;
160 R_FIFO_RESETn : Out std_logic;
161 R_FIFO_RETRANSMITn : Out std_logic;
162 R_FIFO_WRITEn : Out std_logic;
163 RESERVE : Out std_logic;
164 S_ERROR : Out std_logic;
165 S_FIFO_READn : Out std_logic;
166 S_FIFO_RESETn : Out std_logic;
167 S_FIFO_RETRANSMITn : Out std_logic;
168 S_FIFO_WRITEn : Out std_logic;
169 SERIAL_OUT : Out std_logic;
170 SPC_RDY_OUT : Out std_logic;
171 SR_ERROR : Out std_logic;
172 PAR_SER_IN : Out std_logic_vector (7 downto 0);
173 SER_PAR_OUT : Out std_logic_vector (7 downto 0);
174 SYNC_FLAG : Out std_logic_vector (7 downto 0) );
175 end component;
176
177 component PCI_TOP
178 Port ( FLAG : In std_logic_vector (7 downto 0);
179 INT_REG : In std_logic_vector (7 downto 0);
180 PCI_CBEn : In std_logic_vector (3 downto 0);
181 PCI_CLOCK : In std_logic;
182 PCI_FRAMEn : In std_logic;
183 PCI_IDSEL : In std_logic;
184 PCI_IRDYn : In std_logic;
185 PCI_RSTn : In std_logic;
186 R_FIFO_Q : In std_logic_vector (7 downto 0);
187 REVISON_ID : In std_logic_vector (7 downto 0);
188 VENDOR_ID : In std_logic_vector (15 downto 0);
189 PCI_AD : InOut std_logic_vector (31 downto 0);
190 PCI_PAR : InOut std_logic;
191 AD_REG : Out std_logic_vector (31 downto 0);
192 DEVSELn : Out std_logic;
193 FIFO_RDn : Out std_logic;
194 PCI_DEVSELn : Out std_logic;
195 PCI_PERRn : Out std_logic;
196 PCI_SERRn : Out std_logic;
197 PCI_STOPn : Out std_logic;
198 PCI_TRDYn : Out std_logic;
199 READ_SEL : Out std_logic_vector (1 downto 0);
200 READ_XX1_0 : Out std_logic;
201 READ_XX3_2 : Out std_logic;
202 READ_XX5_4 : Out std_logic;
203 READ_XX7_6 : Out std_logic;
204 REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
205 REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
206 REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
207 TRDYn : Out std_logic;
208 WRITE_XX1_0 : Out std_logic;
209 WRITE_XX3_2 : Out std_logic;
210 WRITE_XX5_4 : Out std_logic;
211 WRITE_XX7_6 : Out std_logic );
212 end component;
213
214 component fifo_generator_v3_2
215 port (
216 clk: IN std_logic;
217 din: IN std_logic_VECTOR(7 downto 0);
218 rd_en: IN std_logic;
219 rst: IN std_logic;
220 wr_en: IN std_logic;
221 almost_empty: OUT std_logic;
222 almost_full: OUT std_logic;
223 dout: OUT std_logic_VECTOR(7 downto 0);
224 empty: OUT std_logic;
225 full: OUT std_logic;
226 prog_full: OUT std_logic);
227 end component;
228
229 component icon
230 port
231 (
232 control0 : out std_logic_vector(35 downto 0)
233 );
234 end component;
235
236 component ila
237 port
238 (
239 control : in std_logic_vector(35 downto 0);
240 clk : in std_logic;
241 data : in std_logic_vector(35 downto 0);
242 trig0 : in std_logic_vector(7 downto 0)
243 );
244 end component;
245
246
247 begin
248 SERIAL_IN <= SERIAL_OUT;
249 SPC_RDY_IN <= SPC_RDY_OUT;
250 LED_2 <= TAST_RESn;
251 LED_3 <= TAST_SETn;
252 LED_4 <= '0';
253 LED_5 <= not watch;
254 PCI_INTAn <= watch;
255 trig0(7 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');
256 data(0) <= watch;
257
258 data(1) <= R_EFn;
259 data(2) <= R_HFn;
260 data(3) <= R_FFn;
261 data(4) <= R_FIFO_READn;
262 data(5) <= R_FIFO_RESETn;
263 data(6) <= R_FIFO_RTn;
264 data(7) <= R_FIFO_WRITEn;
265 data(8) <= S_EFn;
266 data(9) <= S_HFn;
267 data(10) <= S_FFn;
268 data(11) <= S_FIFO_READn;
269 data(12) <= S_FIFO_RESETn;
270 data(13) <= S_FIFO_RTn;
271 data(14) <= S_FIFO_WRITEn;
272 data(15) <= SERIAL_IN;
273 data(16) <= SPC_RDY_IN;
274 data(17) <= SERIAL_OUT;
275 data(18) <= SPC_RDY_OUT;
276 data(34 downto 27) <= R_FIFO_Q_OUT;
277
278 I19 : MESS_1_TB
279 Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
280 PCI_IDSEL=>PCI_IDSEL,
281 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
282 TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,
283 TB_PCI_IDSEL=>TB_IDSEL );
284 I18 : VEN_REV_ID
285 Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),
286 VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );
287 I16 : INTERRUPT
288 Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),
289 INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,
290 INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,
291 INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),
292 INT_RES(7 downto 0)=>AD_REG(7 downto 0),
293 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
294 READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),
295 TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,
296 TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),
297 INTAn=>INTAn, PCI_INTAn=>watch);
298 I14 : FIFO_CONTROL
299 Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,
300 FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,
301 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),
302 R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,
303 RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,
304 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
305 S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,
306 SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,
307 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
308 R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
309 R_FIFO_READn=>R_FIFO_READn,
310 R_FIFO_RESETn=>R_FIFO_RESETn,
311 R_FIFO_RETRANSMITn=>R_FIFO_RTn,
312 R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,
313 S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,
314 S_FIFO_RESETn=>S_FIFO_RESETn,
315 S_FIFO_RETRANSMITn=>S_FIFO_RTn,
316 S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,
317 SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,
318 PAR_SER_IN(7 downto 0)=>data(26 downto 19),
319 SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );
320 I1 : PCI_TOP
321 Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),
322 INT_REG(7 downto 0)=>INT_REG(7 downto 0),
323 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
324 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
325 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
326 PCI_RSTn=>PCI_RSTn,
327 R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),
328 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
329 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
330 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
331 PCI_PAR=>PCI_PAR,
332 AD_REG(31 downto 0)=>AD_REG(31 downto 0),
333 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
334 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,
335 PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,
336 PCI_TRDYn=>PCI_TRDYn,
337 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
338 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
339 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,
340 REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),
341 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
342 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
343 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,
344 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
345 WRITE_XX7_6=>WRITE_XX7_6 );
346
347 receive_fifo : fifo_generator_v3_2
348 port map (
349 clk => PCI_CLOCK,
350 din => R_FIFO_D_IN,
351 rd_en => not R_FIFO_READn,
352 rst => not R_FIFO_RESETn,
353 wr_en => not R_FIFO_WRITEn,
354 dout => R_FIFO_Q_OUT,
355 empty => R_EFn,
356 full => R_FFn,
357 prog_full => R_HFn);
358
359 send_fifo : fifo_generator_v3_2
360 port map (
361 clk => PCI_CLOCK,
362 din => S_FIFO_D_IN,
363 rd_en => not S_FIFO_READn,
364 rst => not S_FIFO_RESETn,
365 wr_en => not S_FIFO_WRITEn,
366 dout => S_FIFO_Q_OUT,
367 empty => S_EFn,
368 full => S_FFn,
369 prog_full => S_HFn);
370
371 i_icon : icon
372 port map
373 (
374 control0 => control0
375 );
376
377 i_ila : ila
378 port map
379 (
380 control => control0,
381 clk => PCI_CLOCK,
382 data => data,
383 trig0 => trig0
384 );
385 end SCHEMATIC;
Impressum, Datenschutz