2e73dcb49eeb668cdcfadd50c0fed2366ee3a0c6
[raggedstone] / dhwk / source / user_io.vhd
1 -- VHDL model created from schematic user_io.sch -- Jan 09 09:34:12 2007
2
3 LIBRARY ieee;
4
5 USE ieee.std_logic_1164.ALL;
6 USE ieee.numeric_std.ALL;
7
8
9 entity USER_IO is
10 Port ( AD_REG : In std_logic_vector (31 downto 0);
11 ADDR_REG : In std_logic_vector (31 downto 0);
12 CBE_REGn : In std_logic_vector (3 downto 0);
13 FLAG : In std_logic_vector (7 downto 0);
14 INT_REG : In std_logic_vector (7 downto 0);
15 IO_WR_COM : In std_logic;
16 IRDY_REGn : In std_logic;
17 PCI_CLK : In std_logic;
18 R_FIFO_Q : In std_logic_vector (7 downto 0);
19 READ_SEL : In std_logic_vector (1 downto 0);
20 TRDYn : In std_logic;
21 READ_XX1_0 : Out std_logic;
22 READ_XX3_2 : Out std_logic;
23 READ_XX5_4 : Out std_logic;
24 READ_XX7_6 : Out std_logic;
25 REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
26 REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
27 REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
28 USER_DATA_OUT : Out std_logic_vector (31 downto 0);
29 WRITE_XX1_0 : Out std_logic;
30 WRITE_XX3_2 : Out std_logic;
31 WRITE_XX5_4 : Out std_logic;
32 WRITE_XX7_6 : Out std_logic );
33 end USER_IO;
34
35 architecture SCHEMATIC of USER_IO is
36
37 SIGNAL gnd : std_logic := '0';
38 SIGNAL vcc : std_logic := '1';
39
40 signal WRITE_XX1_0_DUMMY : std_logic;
41 signal WRITE_XX7_6_DUMMY : std_logic;
42 signal REG_OUT_XX7_DUMMY : std_logic_vector (7 downto 0);
43 signal REG_OUT_XX6_DUMMY : std_logic_vector (7 downto 0);
44 signal REG_OUT_XX0_DUMMY : std_logic_vector (7 downto 0);
45
46 component IO_WR_SEL
47 Port ( ADDR_REG : In std_logic_vector (31 downto 0);
48 CBE_REGn : In std_logic_vector (3 downto 0);
49 IO_WR_COM : In std_logic;
50 IRDY_REGn : In std_logic;
51 TRDYn : In std_logic;
52 WRITE_XX1_0 : Out std_logic;
53 WRITE_XX3_2 : Out std_logic;
54 WRITE_XX5_4 : Out std_logic;
55 WRITE_XX7_6 : Out std_logic );
56 end component;
57
58 component DATA_MUX
59 Port ( ADDR_REG : In std_logic_vector (31 downto 0);
60 CBE_REGn : In std_logic_vector (3 downto 0);
61 MUX_IN_XX0 : In std_logic_vector (7 downto 0);
62 MUX_IN_XX1 : In std_logic_vector (7 downto 0);
63 MUX_IN_XX2 : In std_logic_vector (7 downto 0);
64 MUX_IN_XX3 : In std_logic_vector (7 downto 0);
65 MUX_IN_XX4 : In std_logic_vector (7 downto 0);
66 MUX_IN_XX5 : In std_logic_vector (7 downto 0);
67 MUX_IN_XX6 : In std_logic_vector (7 downto 0);
68 MUX_IN_XX7 : In std_logic_vector (7 downto 0);
69 READ_SEL : In std_logic_vector (1 downto 0);
70 MUX_OUT : Out std_logic_vector (31 downto 0);
71 READ_XX1_0 : Out std_logic;
72 READ_XX3_2 : Out std_logic;
73 READ_XX5_4 : Out std_logic;
74 READ_XX7_6 : Out std_logic );
75 end component;
76
77 component REG_IO
78 Port ( AD_REG : In std_logic_vector (31 downto 0);
79 PCI_CLOCK : In std_logic;
80 RESET : In std_logic;
81 WRITE_XX1_0 : In std_logic;
82 WRITE_XX7_6 : In std_logic;
83 REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
84 REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
85 REG_OUT_XX7 : Out std_logic_vector (7 downto 0) );
86 end component;
87
88 begin
89
90 REG_OUT_XX0 <= REG_OUT_XX0_DUMMY;
91 REG_OUT_XX6 <= REG_OUT_XX6_DUMMY;
92 REG_OUT_XX7 <= REG_OUT_XX7_DUMMY;
93 WRITE_XX7_6 <= WRITE_XX7_6_DUMMY;
94 WRITE_XX1_0 <= WRITE_XX1_0_DUMMY;
95
96 I4 : IO_WR_SEL
97 Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
98 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
99 IO_WR_COM=>IO_WR_COM, IRDY_REGn=>IRDY_REGn,
100 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0_DUMMY,
101 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
102 WRITE_XX7_6=>WRITE_XX7_6_DUMMY );
103 I2 : DATA_MUX
104 Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
105 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),
106 MUX_IN_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),
107 MUX_IN_XX1(7 downto 0)=>FLAG(7 downto 0),
108 MUX_IN_XX2(7 downto 0)=>R_FIFO_Q(7 downto 0),
109 MUX_IN_XX3(7 downto 0)=>FLAG(7 downto 0),
110 MUX_IN_XX4(7 downto 0)=>INT_REG(7 downto 0),
111 MUX_IN_XX5(7 downto 0)=>FLAG(7 downto 0),
112 MUX_IN_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),
113 MUX_IN_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0),
114 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
115 MUX_OUT(31 downto 0)=>USER_DATA_OUT(31 downto 0),
116 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
117 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6 );
118 I1 : REG_IO
119 Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),
120 PCI_CLOCK=>PCI_CLK, RESET=>REG_OUT_XX7_DUMMY(0),
121 WRITE_XX1_0=>WRITE_XX1_0_DUMMY,
122 WRITE_XX7_6=>WRITE_XX7_6_DUMMY,
123 REG_OUT_XX0(7 downto 0)=>REG_OUT_XX0_DUMMY(7 downto 0),
124 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6_DUMMY(7 downto 0),
125 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7_DUMMY(7 downto 0) );
126
127 end SCHEMATIC;
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