1 //////////////////////////////////////////////////////////////////////
3 //// eth_rxstatem.v ////
5 //// This file is part of the Ethernet IP core project ////
6 //// http://www.opencores.org/projects/ethmac/ ////
9 //// - Igor Mohor (igorM@opencores.org) ////
10 //// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
11 //// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
13 //// All additional information is avaliable in the Readme.txt ////
16 //////////////////////////////////////////////////////////////////////
18 //// Copyright (C) 2001 Authors ////
20 //// This source file may be used and distributed without ////
21 //// restriction provided that this copyright statement is not ////
22 //// removed from the file and that any derivative work contains ////
23 //// the original copyright notice and the associated disclaimer. ////
25 //// This source file is free software; you can redistribute it ////
26 //// and/or modify it under the terms of the GNU Lesser General ////
27 //// Public License as published by the Free Software Foundation; ////
28 //// either version 2.1 of the License, or (at your option) any ////
29 //// later version. ////
31 //// This source is distributed in the hope that it will be ////
32 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
33 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
34 //// PURPOSE. See the GNU Lesser General Public License for more ////
37 //// You should have received a copy of the GNU Lesser General ////
38 //// Public License along with this source; if not, download it ////
39 //// from http://www.opencores.org/lgpl.shtml ////
41 //////////////////////////////////////////////////////////////////////
43 // CVS Revision History
45 // $Log: eth_rxstatem.v,v $
46 // Revision 1.1 2007-03-20 17:50:56 sithglan
49 // Revision 1.6 2002/11/13 22:28:26 tadejm
50 // StartIdle state changed (not important the size of the packet).
51 // StartData1 activates only while ByteCnt is smaller than the MaxFrame.
53 // Revision 1.5 2002/01/23 10:28:16 mohor
54 // Link in the header changed.
56 // Revision 1.4 2001/10/19 08:43:51 mohor
57 // eth_timescale.v changed to timescale.v This is done because of the
58 // simulation of the few cores in a one joined project.
60 // Revision 1.3 2001/10/18 12:07:11 mohor
61 // Status signals changed, Adress decoding changed, interrupt controller
64 // Revision 1.2 2001/09/11 14:17:00 mohor
65 // Few little NCSIM warnings fixed.
67 // Revision 1.1 2001/08/06 14:44:29 mohor
68 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
69 // Include files fixed to contain no path.
70 // File names and module names changed ta have a eth_ prologue in the name.
71 // File eth_timescale.v is used to define timescale
72 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
73 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
74 // and Mdo_OE. The bidirectional signal must be created on the top level. This
75 // is done due to the ASIC tools.
77 // Revision 1.1 2001/07/30 21:23:42 mohor
78 // Directory structure changed. Files checked and joind together.
80 // Revision 1.2 2001/07/03 12:55:41 mohor
81 // Minor changes because of the synthesys warnings.
84 // Revision 1.1 2001/06/27 21:26:19 mohor
85 // Initial release of the RxEthMAC module.
92 `include "timescale.v"
95 module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,
96 IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD,
110 input IFGCounterEq24;
111 input ByteCntMaxFrame;
113 output [1:0] StateData;
116 output StatePreamble;
134 // Defining the next state
135 assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData));
137 assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);
139 assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting | StatePreamble);
141 assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1);
143 assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame);
145 assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 & MRxDEqD
146 | StateData0 & ByteCntMaxFrame
150 always @ (posedge MRxClk or posedge Reset)
154 StateIdle <= #Tp 1'b0;
155 StateDrop <= #Tp 1'b1;
156 StatePreamble <= #Tp 1'b0;
157 StateSFD <= #Tp 1'b0;
158 StateData0 <= #Tp 1'b0;
159 StateData1 <= #Tp 1'b0;
163 if(StartPreamble | StartSFD | StartDrop)
164 StateIdle <= #Tp 1'b0;
167 StateIdle <= #Tp 1'b1;
170 StateDrop <= #Tp 1'b0;
173 StateDrop <= #Tp 1'b1;
175 if(StartSFD | StartIdle | StartDrop)
176 StatePreamble <= #Tp 1'b0;
179 StatePreamble <= #Tp 1'b1;
181 if(StartPreamble | StartIdle | StartData0 | StartDrop)
182 StateSFD <= #Tp 1'b0;
185 StateSFD <= #Tp 1'b1;
187 if(StartIdle | StartData1 | StartDrop)
188 StateData0 <= #Tp 1'b0;
191 StateData0 <= #Tp 1'b1;
193 if(StartIdle | StartData0 | StartDrop)
194 StateData1 <= #Tp 1'b0;
197 StateData1 <= #Tp 1'b1;
201 assign StateData[1:0] = {StateData1, StateData0};