add shit
[raggedstone] / ethernet / ethernet.prj
1 vhdl work "source/ethernet/eth_crc.v"
2 vhdl work "source/ethernet/eth_cop.v"
3 vhdl work "source/ethernet/eth_maccontrol.v"
4 vhdl work "source/ethernet/eth_register.v"
5 vhdl work "source/ethernet/eth_fifo.v"
6 vhdl work "source/ethernet/eth_rxstatem.v"
7 vhdl work "source/ethernet/eth_txcounters.v"
8 vhdl work "source/ethernet/eth_random.v"
9 vhdl work "source/ethernet/eth_rxcounters.v"
10 vhdl work "source/ethernet/eth_top.v"
11 vhdl work "source/ethernet/eth_shiftreg.v"
12 vhdl work "source/ethernet/eth_miim.v"
13 vhdl work "source/ethernet/eth_wishbone.v"
14 vhdl work "source/ethernet/eth_rxaddrcheck.v"
15 vhdl work "source/ethernet/xilinx_dist_ram_16x32.v"
16 vhdl work "source/ethernet/eth_spram_256x32.v"
17 vhdl work "source/ethernet/eth_txethmac.v"
18 vhdl work "source/ethernet/timescale.v"
19 vhdl work "source/ethernet/eth_registers.v"
20 vhdl work "source/ethernet/eth_defines.v"
21 vhdl work "source/ethernet/eth_rxethmac.v"
22 vhdl work "source/ethernet/eth_receivecontrol.v"
23 vhdl work "source/ethernet/eth_outputcontrol.v"
24 vhdl work "source/ethernet/eth_txstatem.v"
25 vhdl work "source/ethernet/eth_transmitcontrol.v"
26 vhdl work "source/ethernet/eth_macstatus.v"
27 vhdl work "source/ethernet/eth_clockgen.v"
28 vhdl work "source/pci/pci_target_unit.v"
29 vhdl work "source/pci/pci_target32_stop_crit.v"
30 vhdl work "source/pci/pci_delayed_sync.v"
31 vhdl work "source/pci/pci_wb_slave_unit.v"
32 vhdl work "source/pci/pci_frame_load_crit.v"
33 vhdl work "source/pci/pci_mas_ad_en_crit.v"
34 vhdl work "source/pci/pci_constants.v"
35 vhdl work "source/pci/pci_wbw_wbr_fifos.v"
36 vhdl work "source/pci/pci_wb_slave.v"
37 vhdl work "source/pci/pci_target32_trdy_crit.v"
38 vhdl work "source/pci/pci_target32_interface.v"
39 vhdl work "source/pci/pci_wbw_fifo_control.v"
40 vhdl work "source/pci/pci_wb_tpram.v"
41 vhdl work "source/pci/pci_par_crit.v"
42 vhdl work "source/pci/pci_conf_space.v"
43 vhdl work "source/pci/pci_target32_sm.v"
44 vhdl work "source/pci/pci_pciw_pcir_fifos.v"
45 vhdl work "source/pci/pci_serr_en_crit.v"
46 vhdl work "source/pci/pci_target32_devs_crit.v"
47 vhdl work "source/pci/pci_out_reg.v"
48 vhdl work "source/pci/pci_mas_ad_load_crit.v"
49 vhdl work "source/pci/pci_delayed_write_reg.v"
50 vhdl work "source/pci/pci_wbs_wbb3_2_wbb2.v"
51 vhdl work "source/pci/pci_wb_master.v"
52 vhdl work "source/pci/bus_commands.v"
53 vhdl work "source/pci/pci_rst_int.v"
54 vhdl work "source/pci/pci_sync_module.v"
55 vhdl work "source/pci/pci_master32_sm_if.v"
56 vhdl work "source/pci/pci_frame_crit.v"
57 vhdl work "source/pci/pci_user_constants.v"
58 vhdl work "source/pci/pci_io_mux_ad_load_crit.v"
59 vhdl work "source/pci/pci_pciw_fifo_control.v"
60 vhdl work "source/pci/pci_parity_check.v"
61 vhdl work "source/pci/pci_irdy_out_crit.v"
62 vhdl work "source/pci/pci_perr_crit.v"
63 vhdl work "source/pci/pci_mas_ch_state_crit.v"
64 vhdl work "source/pci/pci_spoci_ctrl.v"
65 vhdl work "source/pci/pci_wb_addr_mux.v"
66 vhdl work "source/pci/pci_perr_en_crit.v"
67 vhdl work "source/pci/pci_target32_clk_en.v"
68 vhdl work "source/pci/timescale.v"
69 vhdl work "source/pci/pci_serr_crit.v"
70 vhdl work "source/pci/pci_frame_en_crit.v"
71 vhdl work "source/pci/pci_master32_sm.v"
72 vhdl work "source/pci/pci_pci_tpram.v"
73 vhdl work "source/pci/pci_cur_out_reg.v"
74 vhdl work "source/pci/pci_io_mux.v"
75 vhdl work "source/pci/pci_wbr_fifo_control.v"
76 vhdl work "source/pci/pci_ram_16x40d.v"
77 vhdl work "source/pci/pci_io_mux_ad_en_crit.v"
78 vhdl work "source/pci/pci_async_reset_flop.v"
79 vhdl work "source/pci/pci_wb_decoder.v"
80 vhdl work "source/pci/pci_conf_cyc_addr_dec.v"
81 vhdl work "source/pci/pci_bridge32.v"
82 vhdl work "source/pci/pci_synchronizer_flop.v"
83 vhdl work "source/pci/pci_pcir_fifo_control.v"
84 vhdl work "source/pci/pci_cbe_en_crit.v"
85 vhdl work "source/pci/pci_pci_decoder.v"
86 vhdl work "source/pci/pci_in_reg.v"
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