add shit
[raggedstone] / ethernet / source / ethernet / eth_maccontrol.v
1 //////////////////////////////////////////////////////////////////////
2 //// ////
3 //// eth_maccontrol.v ////
4 //// ////
5 //// This file is part of the Ethernet IP core project ////
6 //// http://www.opencores.org/projects/ethmac/ ////
7 //// ////
8 //// Author(s): ////
9 //// - Igor Mohor (igorM@opencores.org) ////
10 //// ////
11 //// All additional information is avaliable in the Readme.txt ////
12 //// file. ////
13 //// ////
14 //////////////////////////////////////////////////////////////////////
15 //// ////
16 //// Copyright (C) 2001 Authors ////
17 //// ////
18 //// This source file may be used and distributed without ////
19 //// restriction provided that this copyright statement is not ////
20 //// removed from the file and that any derivative work contains ////
21 //// the original copyright notice and the associated disclaimer. ////
22 //// ////
23 //// This source file is free software; you can redistribute it ////
24 //// and/or modify it under the terms of the GNU Lesser General ////
25 //// Public License as published by the Free Software Foundation; ////
26 //// either version 2.1 of the License, or (at your option) any ////
27 //// later version. ////
28 //// ////
29 //// This source is distributed in the hope that it will be ////
30 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
31 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
32 //// PURPOSE. See the GNU Lesser General Public License for more ////
33 //// details. ////
34 //// ////
35 //// You should have received a copy of the GNU Lesser General ////
36 //// Public License along with this source; if not, download it ////
37 //// from http://www.opencores.org/lgpl.shtml ////
38 //// ////
39 //////////////////////////////////////////////////////////////////////
40 //
41 // CVS Revision History
42 //
43 // $Log: eth_maccontrol.v,v $
44 // Revision 1.1 2007-03-20 17:50:56 sithglan
45 // add shit
46 //
47 // Revision 1.7 2003/01/22 13:49:26 tadejm
48 // When control packets were received, they were ignored in some cases.
49 //
50 // Revision 1.6 2002/11/22 01:57:06 mohor
51 // Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
52 // synchronized.
53 //
54 // Revision 1.5 2002/11/21 00:14:39 mohor
55 // TxDone and TxAbort changed so they're not propagated to the wishbone
56 // module when control frame is transmitted.
57 //
58 // Revision 1.4 2002/11/19 17:37:32 mohor
59 // When control frame (PAUSE) was sent, status was written in the
60 // eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
61 // Only TXC interrupt is set.
62 //
63 // Revision 1.3 2002/01/23 10:28:16 mohor
64 // Link in the header changed.
65 //
66 // Revision 1.2 2001/10/19 08:43:51 mohor
67 // eth_timescale.v changed to timescale.v This is done because of the
68 // simulation of the few cores in a one joined project.
69 //
70 // Revision 1.1 2001/08/06 14:44:29 mohor
71 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
72 // Include files fixed to contain no path.
73 // File names and module names changed ta have a eth_ prologue in the name.
74 // File eth_timescale.v is used to define timescale
75 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
76 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
77 // and Mdo_OE. The bidirectional signal must be created on the top level. This
78 // is done due to the ASIC tools.
79 //
80 // Revision 1.1 2001/07/30 21:23:42 mohor
81 // Directory structure changed. Files checked and joind together.
82 //
83 // Revision 1.1 2001/07/03 12:51:54 mohor
84 // Initial release of the MAC Control module.
85 //
86 //
87 //
88 //
89
90
91 `include "timescale.v"
92
93
94 module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn,
95 TxEndFrmIn, TxDoneIn, TxAbortIn, RxData, RxValid, RxStartFrm, RxEndFrm, ReceiveEnd,
96 ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, DlyCrcEn, TxPauseTV,
97 MAC, PadIn, PadOut, CrcEnIn, CrcEnOut, TxDataOut, TxStartFrmOut, TxEndFrmOut,
98 TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm,
99 ReceivedPauseFrm, ControlFrmAddressOK, SetPauseTimer, r_PassAll, RxStatusWriteLatched_sync2
100 );
101
102
103 parameter Tp = 1;
104
105
106 input MTxClk; // Transmit clock (from PHY)
107 input MRxClk; // Receive clock (from PHY)
108 input TxReset; // Transmit reset
109 input RxReset; // Receive reset
110 input TPauseRq; // Transmit control frame (from host)
111 input [7:0] TxDataIn; // Transmit packet data byte (from host)
112 input TxStartFrmIn; // Transmit packet start frame input (from host)
113 input TxUsedDataIn; // Transmit packet used data (from TxEthMAC)
114 input TxEndFrmIn; // Transmit packet end frame input (from host)
115 input TxDoneIn; // Transmit packet done (from TxEthMAC)
116 input TxAbortIn; // Transmit packet abort (input from TxEthMAC)
117 input PadIn; // Padding (input from registers)
118 input CrcEnIn; // Crc append (input from registers)
119 input [7:0] RxData; // Receive Packet Data (from RxEthMAC)
120 input RxValid; // Received a valid packet
121 input RxStartFrm; // Receive packet start frame (input from RxEthMAC)
122 input RxEndFrm; // Receive packet end frame (input from RxEthMAC)
123 input ReceiveEnd; // End of receiving of the current packet (input from RxEthMAC)
124 input ReceivedPacketGood; // Received packet is good
125 input ReceivedLengthOK; // Length of the received packet is OK
126 input TxFlow; // Tx flow control (from registers)
127 input RxFlow; // Rx flow control (from registers)
128 input DlyCrcEn; // Delayed CRC enabled (from registers)
129 input [15:0] TxPauseTV; // Transmit Pause Timer Value (from registers)
130 input [47:0] MAC; // MAC address (from registers)
131 input RxStatusWriteLatched_sync2;
132 input r_PassAll;
133
134 output [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
135 output TxStartFrmOut; // Transmit packet start frame (output to TxEthMAC)
136 output TxEndFrmOut; // Transmit packet end frame (output to TxEthMAC)
137 output TxDoneOut; // Transmit packet done (to host)
138 output TxAbortOut; // Transmit packet aborted (to host)
139 output TxUsedDataOut; // Transmit packet used data (to host)
140 output PadOut; // Padding (output to TxEthMAC)
141 output CrcEnOut; // Crc append (output to TxEthMAC)
142 output WillSendControlFrame;
143 output TxCtrlEndFrm;
144 output ReceivedPauseFrm;
145 output ControlFrmAddressOK;
146 output SetPauseTimer;
147
148 reg TxUsedDataOutDetected;
149 reg TxAbortInLatched;
150 reg TxDoneInLatched;
151 reg MuxedDone;
152 reg MuxedAbort;
153
154 wire Pause;
155 wire TxCtrlStartFrm;
156 wire [7:0] ControlData;
157 wire CtrlMux;
158 wire SendingCtrlFrm; // Sending Control Frame (enables padding and CRC)
159 wire BlockTxDone;
160
161
162 // Signal TxUsedDataOut was detected (a transfer is already in progress)
163 always @ (posedge MTxClk or posedge TxReset)
164 begin
165 if(TxReset)
166 TxUsedDataOutDetected <= #Tp 1'b0;
167 else
168 if(TxDoneIn | TxAbortIn)
169 TxUsedDataOutDetected <= #Tp 1'b0;
170 else
171 if(TxUsedDataOut)
172 TxUsedDataOutDetected <= #Tp 1'b1;
173 end
174
175
176 // Latching variables
177 always @ (posedge MTxClk or posedge TxReset)
178 begin
179 if(TxReset)
180 begin
181 TxAbortInLatched <= #Tp 1'b0;
182 TxDoneInLatched <= #Tp 1'b0;
183 end
184 else
185 begin
186 TxAbortInLatched <= #Tp TxAbortIn;
187 TxDoneInLatched <= #Tp TxDoneIn;
188 end
189 end
190
191
192
193 // Generating muxed abort signal
194 always @ (posedge MTxClk or posedge TxReset)
195 begin
196 if(TxReset)
197 MuxedAbort <= #Tp 1'b0;
198 else
199 if(TxStartFrmIn)
200 MuxedAbort <= #Tp 1'b0;
201 else
202 if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected)
203 MuxedAbort <= #Tp 1'b1;
204 end
205
206
207 // Generating muxed done signal
208 always @ (posedge MTxClk or posedge TxReset)
209 begin
210 if(TxReset)
211 MuxedDone <= #Tp 1'b0;
212 else
213 if(TxStartFrmIn)
214 MuxedDone <= #Tp 1'b0;
215 else
216 if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected)
217 MuxedDone <= #Tp 1'b1;
218 end
219
220
221 // TxDoneOut
222 assign TxDoneOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedDone) :
223 ((~TxStartFrmIn) & (~BlockTxDone) & TxDoneIn);
224
225 // TxAbortOut
226 assign TxAbortOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedAbort) :
227 ((~TxStartFrmIn) & (~BlockTxDone) & TxAbortIn);
228
229 // TxUsedDataOut
230 assign TxUsedDataOut = ~CtrlMux & TxUsedDataIn;
231
232 // TxStartFrmOut
233 assign TxStartFrmOut = CtrlMux? TxCtrlStartFrm : (TxStartFrmIn & ~Pause);
234
235
236 // TxEndFrmOut
237 assign TxEndFrmOut = CtrlMux? TxCtrlEndFrm : TxEndFrmIn;
238
239
240 // TxDataOut[7:0]
241 assign TxDataOut[7:0] = CtrlMux? ControlData[7:0] : TxDataIn[7:0];
242
243
244 // PadOut
245 assign PadOut = PadIn | SendingCtrlFrm;
246
247
248 // CrcEnOut
249 assign CrcEnOut = CrcEnIn | SendingCtrlFrm;
250
251
252
253 // Connecting receivecontrol module
254 eth_receivecontrol receivecontrol1
255 (
256 .MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData),
257 .RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow),
258 .ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn),
259 .TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK),
260 .ReceivedPacketGood(ReceivedPacketGood), .TxUsedDataOutDetected(TxUsedDataOutDetected),
261 .Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK),
262 .r_PassAll(r_PassAll), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .SetPauseTimer(SetPauseTimer)
263 );
264
265
266 eth_transmitcontrol transmitcontrol1
267 (
268 .MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut),
269 .TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq),
270 .TxUsedDataOutDetected(TxUsedDataOutDetected), .TxFlow(TxFlow), .DlyCrcEn(DlyCrcEn), .TxPauseTV(TxPauseTV),
271 .MAC(MAC), .TxCtrlStartFrm(TxCtrlStartFrm), .TxCtrlEndFrm(TxCtrlEndFrm), .SendingCtrlFrm(SendingCtrlFrm),
272 .CtrlMux(CtrlMux), .ControlData(ControlData), .WillSendControlFrame(WillSendControlFrame), .BlockTxDone(BlockTxDone)
273 );
274
275
276
277 endmodule
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