add shit
[raggedstone] / ethernet / source / pci / pci_target32_stop_crit.v
1 //////////////////////////////////////////////////////////////////////
2 //// ////
3 //// File name: pci_target32_stop_crit.v ////
4 //// ////
5 //// This file is part of the "PCI bridge" project ////
6 //// http://www.opencores.org/cores/pci/ ////
7 //// ////
8 //// Author(s): ////
9 //// - Tadej Markovic, tadej@opencores.org ////
10 //// ////
11 //// All additional information is avaliable in the README.txt ////
12 //// file. ////
13 //// ////
14 //// ////
15 //////////////////////////////////////////////////////////////////////
16 //// ////
17 //// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
18 //// ////
19 //// This source file may be used and distributed without ////
20 //// restriction provided that this copyright statement is not ////
21 //// removed from the file and that any derivative work contains ////
22 //// the original copyright notice and the associated disclaimer. ////
23 //// ////
24 //// This source file is free software; you can redistribute it ////
25 //// and/or modify it under the terms of the GNU Lesser General ////
26 //// Public License as published by the Free Software Foundation; ////
27 //// either version 2.1 of the License, or (at your option) any ////
28 //// later version. ////
29 //// ////
30 //// This source is distributed in the hope that it will be ////
31 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
32 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
33 //// PURPOSE. See the GNU Lesser General Public License for more ////
34 //// details. ////
35 //// ////
36 //// You should have received a copy of the GNU Lesser General ////
37 //// Public License along with this source; if not, download it ////
38 //// from http://www.opencores.org/lgpl.shtml ////
39 //// ////
40 //////////////////////////////////////////////////////////////////////
41 //
42 // CVS Revision History
43 //
44 // $Log: pci_target32_stop_crit.v,v $
45 // Revision 1.1 2007-03-20 17:50:56 sithglan
46 // add shit
47 //
48 // Revision 1.4 2003/01/27 16:49:31 mihad
49 // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
50 //
51 // Revision 1.3 2002/02/01 15:25:12 mihad
52 // Repaired a few bugs, updated specification, added test bench files and design document
53 //
54 // Revision 1.2 2001/10/05 08:14:30 mihad
55 // Updated all files with inclusion of timescale file for simulation purposes.
56 //
57 // Revision 1.1.1.1 2001/10/02 15:33:47 mihad
58 // New project directory structure
59 //
60 //
61
62 // module is used to separate logic which uses criticaly constrained inputs from slower logic.
63 // It is used to synthesize critical timing logic separately with faster cells or without optimization
64
65 // synopsys translate_off
66 `include "timescale.v"
67 // synopsys translate_on
68
69 module pci_target32_stop_crit
70 (
71 stop_w,
72 stop_w_frm,
73 stop_w_frm_irdy,
74 pci_frame_in,
75 pci_irdy_in,
76 pci_stop_out
77 );
78
79 input stop_w ; // stop signal (composed without critical signals) that do not need critical inputs
80 input stop_w_frm ; // stop signal (composed without critical signals) that needs AND with critical FRAME input
81 input stop_w_frm_irdy ; // stop signal (composed without critical signals) that needs AND with critical FRAME and
82 // IRDY inputs
83 input pci_frame_in ; // critical constrained input signal
84 input pci_irdy_in ; // critical constrained input signal
85
86 output pci_stop_out ; // PCI stop output
87
88 // PCI stop output with preserved hierarchy for minimum delay!
89 assign pci_stop_out = ~(stop_w || (stop_w_frm && ~pci_frame_in) || (stop_w_frm_irdy && ~pci_frame_in && ~pci_irdy_in)) ;
90
91
92 endmodule
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