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[raggedstone] / ethernet / source / top.vhd
1 entity top is
2 PORT(
3 PCI_AD : INOUT std_logic_vector(31 downto 0);
4 PCI_CLOCK : IN std_logic;
5 PCI_IDSEL : IN std_logic;
6 PCI_CBEn : INOUT std_logic_vector (3 downto 0);
7 PCI_FRAMEn : INOUT std_logic;
8 PCI_IRDYn : INOUT std_logic;
9 PCI_RSTn : INOUT std_logic;
10 PCI_DEVSELn : INOUT std_logic;
11 PCI_INTAn : INOUT std_logic;
12 PCI_PERRn : INOUT std_logic;
13 PCI_SERRn : INOUT std_logic;
14 PCI_STOPn : INOUT std_logic;
15 PCI_TRDYn : INOUT std_logic;
16 PCI_PAR : INOUT std_logic;
17 PCI_REQn : OUT std_logic;
18 PCI_GNTn : IN std_logic;
19
20 MTX_CLK_PAD_I : IN std_logic;
21 MTXD_PAD_O : OUT std_logic_vector (3 downto 0);
22 MTXEN_PAD_O : OUT std_logic;
23 MRX_CLK_PAD_I : IN std_logic;
24 MRXD_PAD_I : IN std_logic_vector (3 downto 0);
25 MRXDV_PAD_I : IN std_logic;
26 MRXERR_PAD_I : IN std_logic;
27 MCOLL_PAD_I : IN std_logic;
28 MCRS_PAD_I : IN std_logic;
29 MD_PAD_IO : INOUT std_logic;
30 MDC_PAD_O : OUT std_logic;
31 );
32 end top;
33
34 architecture bla of top is
35
36 COMPONENT eth_top
37 PORT(
38 wb_clk_i : IN std_logic;
39 wb_rst_i : IN std_logic;
40 wb_dat_i : IN std_logic_vector(31 downto 0);
41 wb_adr_i : IN std_logic_vector(11 downto 2);
42 wb_sel_i : IN std_logic_vector(3 downto 0);
43 wb_we_i : IN std_logic;
44 wb_cyc_i : IN std_logic;
45 wb_stb_i : IN std_logic;
46 m_wb_dat_i : IN std_logic_vector(31 downto 0);
47 m_wb_ack_i : IN std_logic;
48 m_wb_err_i : IN std_logic;
49 mtx_clk_pad_i : IN std_logic;
50 mrx_clk_pad_i : IN std_logic;
51 mrxd_pad_i : IN std_logic_vector(3 downto 0);
52 mrxdv_pad_i : IN std_logic;
53 mrxerr_pad_i : IN std_logic;
54 mcoll_pad_i : IN std_logic;
55 mcrs_pad_i : IN std_logic;
56 md_pad_i : IN std_logic;
57 wb_dat_o : OUT std_logic_vector(31 downto 0);
58 wb_ack_o : OUT std_logic;
59 wb_err_o : OUT std_logic;
60 m_wb_adr_o : OUT std_logic_vector(31 downto 0);
61 m_wb_sel_o : OUT std_logic_vector(3 downto 0);
62 m_wb_we_o : OUT std_logic;
63 m_wb_dat_o : OUT std_logic_vector(31 downto 0);
64 m_wb_cyc_o : OUT std_logic;
65 m_wb_stb_o : OUT std_logic;
66 mtxd_pad_o : OUT std_logic_vector(3 downto 0);
67 mtxen_pad_o : OUT std_logic;
68 mtxerr_pad_o : OUT std_logic;
69 mdc_pad_o : OUT std_logic;
70 md_pad_o : OUT std_logic;
71 md_padoe_o : OUT std_logic;
72 int_o : OUT std_logic
73 );
74 END COMPONENT;
75
76 COMPONENT pci_bridge32
77 PORT(
78 wb_clk_i : IN std_logic;
79 wb_rst_i : IN std_logic;
80 wb_int_i : IN std_logic;
81 wbs_adr_i : IN std_logic_vector(31 downto 0);
82 wbs_dat_i : IN std_logic_vector(31 downto 0);
83 wbs_sel_i : IN std_logic_vector(3 downto 0);
84 wbs_cyc_i : IN std_logic;
85 wbs_stb_i : IN std_logic;
86 wbs_we_i : IN std_logic;
87 wbs_cti_i : IN std_logic_vector(2 downto 0);
88 wbs_bte_i : IN std_logic_vector(1 downto 0);
89 wbm_dat_i : IN std_logic_vector(31 downto 0);
90 wbm_ack_i : IN std_logic;
91 wbm_rty_i : IN std_logic;
92 wbm_err_i : IN std_logic;
93 pci_clk_i : IN std_logic;
94 pci_rst_i : IN std_logic;
95 pci_inta_i : IN std_logic;
96 pci_gnt_i : IN std_logic;
97 pci_frame_i : IN std_logic;
98 pci_irdy_i : IN std_logic;
99 pci_idsel_i : IN std_logic;
100 pci_devsel_i : IN std_logic;
101 pci_trdy_i : IN std_logic;
102 pci_stop_i : IN std_logic;
103 pci_ad_i : IN std_logic_vector(31 downto 0);
104 pci_cbe_i : IN std_logic_vector(3 downto 0);
105 pci_par_i : IN std_logic;
106 pci_perr_i : IN std_logic;
107 wb_rst_o : OUT std_logic;
108 wb_int_o : OUT std_logic;
109 wbs_dat_o : OUT std_logic_vector(31 downto 0);
110 wbs_ack_o : OUT std_logic;
111 wbs_rty_o : OUT std_logic;
112 wbs_err_o : OUT std_logic;
113 wbm_adr_o : OUT std_logic_vector(31 downto 0);
114 wbm_dat_o : OUT std_logic_vector(31 downto 0);
115 wbm_sel_o : OUT std_logic_vector(3 downto 0);
116 wbm_cyc_o : OUT std_logic;
117 wbm_stb_o : OUT std_logic;
118 wbm_we_o : OUT std_logic;
119 wbm_cti_o : OUT std_logic_vector(2 downto 0);
120 wbm_bte_o : OUT std_logic_vector(1 downto 0);
121 pci_rst_o : OUT std_logic;
122 pci_inta_o : OUT std_logic;
123 pci_rst_oe_o : OUT std_logic;
124 pci_inta_oe_o : OUT std_logic;
125 pci_req_o : OUT std_logic;
126 pci_req_oe_o : OUT std_logic;
127 pci_frame_o : OUT std_logic;
128 pci_frame_oe_o : OUT std_logic;
129 pci_irdy_oe_o : OUT std_logic;
130 pci_devsel_oe_o : OUT std_logic;
131 pci_trdy_oe_o : OUT std_logic;
132 pci_stop_oe_o : OUT std_logic;
133 pci_ad_oe_o : OUT std_logic_vector(31 downto 0);
134 pci_cbe_oe_o : OUT std_logic_vector(3 downto 0);
135 pci_irdy_o : OUT std_logic;
136 pci_devsel_o : OUT std_logic;
137 pci_trdy_o : OUT std_logic;
138 pci_stop_o : OUT std_logic;
139 pci_ad_o : OUT std_logic_vector(31 downto 0);
140 pci_cbe_o : OUT std_logic_vector(3 downto 0);
141 pci_par_o : OUT std_logic;
142 pci_par_oe_o : OUT std_logic;
143 pci_perr_o : OUT std_logic;
144 pci_perr_oe_o : OUT std_logic;
145 pci_serr_o : OUT std_logic;
146 pci_serr_oe_o : OUT std_logic
147 );
148 END COMPONENT;
149
150 signal pci_rst_o : std_logic;
151 signal pci_rst_oe_o : std_logic;
152 signal pci_inta_o : std_logic;
153 signal pci_inta_oe_o : std_logic;
154 signal pci_req_o : std_logic;
155 signal pci_req_oe_o : std_logic;
156 signal pci_frame_o : std_logic;
157 signal pci_frame_oe_o : std_logic;
158 signal pci_irdy_o : std_logic;
159 signal pci_irdy_oe_o : std_logic;
160 signal pci_devsel_o : std_logic;
161 signal pci_devsel_oe_o : std_logic;
162 signal pci_trdy_o : std_logic;
163 signal pci_trdy_oe_o : std_logic;
164 signal pci_stop_o : std_logic;
165 signal pci_stop_oe_o : std_logic;
166 signal pci_par_o : std_logic;
167 signal pci_par_oe_o : std_logic;
168 signal pci_perr_o : std_logic;
169 signal pci_perr_oe_o : std_logic;
170 signal pci_serr_o : std_logic;
171 signal pci_serr_oe_o : std_logic;
172 signal pci_ad_oe_o : std_logic;
173 signal pci_cbe_oe_o : std_logic;
174 signal pci_ad_o : std_logic_vector (31 downto 0);
175 signal pci_cbe_o : std_logic_vector (3 downto 0);
176
177 BEGIN
178
179 PCI_RSTn <= if (pci_rst_oe_o = '1') then pci_rst_o else 'Z';
180 PCI_INTAn <= if (pci_inta_oe_o = '1') then pci_inta_o else 'Z';
181 PCI_REQn <= if (pci_req_oe_o = '1') then pci_req_o else 'Z';
182 PCI_FRAMEn <= if (pci_frame_oe_o '1') then pci_frame_o else 'Z';
183 PCI_IRDYn <= if (pci_irdy_oe_o = '1') then pci_irdy_o else 'Z';
184 PCI_DEVSELn <= if (pci_devsel_oe_o = '1') then pci_devsel_o else 'Z';
185 PCI_TRDYn <= if (pci_trdy_oe_o = '1') then pci_trdy_o else 'Z';
186 PCI_STOPn <= if (pci_stop_oe_o = '1') then pci_stop_o else 'Z';
187 PCI_AD <= if (pci_ad_oe_o = '1') then pci_ad_o else (others => 'Z');
188 PCI_CBEn <= if (pci_cbe_oe_o = '1') then pci_cbe_o else (others => 'Z');
189 PCI_PAR <= if (pci_par_oe_o = '1') then pci_par_o else 'Z';
190 PCI_PERRn <= if (pci_perr_oe_o = '1') then pci_perr_o else 'Z';
191 PCI_SERRn <= if (pci_serr_oe_o = '1') then pci_serr_o else 'Z';
192
193 Inst_pci_bridge32: pci_bridge32 PORT MAP(
194 wb_clk_i => ,
195 wb_rst_i => ,
196 wb_rst_o => ,
197 wb_int_i => ,
198 wb_int_o => ,
199 wbs_adr_i => ,
200 wbs_dat_i => ,
201 wbs_dat_o => ,
202 wbs_sel_i => ,
203 wbs_cyc_i => ,
204 wbs_stb_i => ,
205 wbs_we_i => ,
206 wbs_cti_i => ,
207 wbs_bte_i => ,
208 wbs_ack_o => ,
209 wbs_rty_o => ,
210 wbs_err_o => ,
211 wbm_adr_o => ,
212 wbm_dat_i => ,
213 wbm_dat_o => ,
214 wbm_sel_o => ,
215 wbm_cyc_o => ,
216 wbm_stb_o => ,
217 wbm_we_o => ,
218 wbm_cti_o => ,
219 wbm_bte_o => ,
220 wbm_ack_i => ,
221 wbm_rty_i => ,
222 wbm_err_i => ,
223 pci_clk_i => PCI_CLOCK,
224 pci_rst_i => PCI_RSTn,
225 pci_rst_o => pci_rst_o ,
226 pci_rst_oe_o => pci_rst_oe_o,
227 pci_inta_i => PCI_INTAn,
228 pci_inta_o => pci_inta_o,
229 pci_inta_oe_o => pci_inta_oe_o,
230 pci_req_o => pci_req_o,
231 pci_req_oe_o => pci_req_oe_o,
232 pci_gnt_i => PCI_GNTn,
233 pci_frame_i => PCI_FRAMEn,
234 pci_frame_o => pci_frame_o,
235 pci_frame_oe_o => pci_frame_oe_o,
236 pci_irdy_oe_o => pci_irdy_oe_o,
237 pci_devsel_oe_o => pci_devsel_oe_o,
238 pci_trdy_oe_o => pci_trdy_oe_o,
239 pci_stop_oe_o => pci_stop_oe_o,
240 pci_ad_oe_o => pci_ad_oe_o,
241 pci_cbe_oe_o => pci_cbe_oe_o,
242 pci_irdy_i => PCI_IRDYn,
243 pci_irdy_o => pci_irdy_o,
244 pci_idsel_i => PCI_IDSEL,
245 pci_devsel_i => PCI_DEVSELn,
246 pci_devsel_o => pci_devsel_o,
247 pci_trdy_i => PCI_TRDYn,
248 pci_trdy_o => pci_trdy_o,
249 pci_stop_i => PCI_STOPn,
250 pci_stop_o => pci_stop_o,
251 pci_ad_i => PCI_AD,
252 pci_ad_o => pci_ad_o,
253 pci_cbe_i => PCI_CBEn,
254 pci_cbe_o => pci_cbe_o,
255 pci_par_i => PCI_PAR,
256 pci_par_o => pci_par_o,
257 pci_par_oe_o => pci_par_oe_o,
258 pci_perr_i => PCI_PERRn,
259 pci_perr_o => pci_perr_o,
260 pci_perr_oe_o => pci_perr_oe_o,
261 pci_serr_o => pci_serr_o,
262 pci_serr_oe_o => pci_serr_oe_o
263 );
264
265 Inst_eth_top: eth_top PORT MAP(
266 wb_clk_i => ,
267 wb_rst_i => ,
268 wb_dat_i => ,
269 wb_dat_o => ,
270 wb_adr_i => ,
271 wb_sel_i => ,
272 wb_we_i => ,
273 wb_cyc_i => ,
274 wb_stb_i => ,
275 wb_ack_o => ,
276 wb_err_o => ,
277 m_wb_adr_o => ,
278 m_wb_sel_o => ,
279 m_wb_we_o => ,
280 m_wb_dat_o => ,
281 m_wb_dat_i => ,
282 m_wb_cyc_o => ,
283 m_wb_stb_o => ,
284 m_wb_ack_i => ,
285 m_wb_err_i => ,
286 mtx_clk_pad_i => ,
287 mtxd_pad_o => ,
288 mtxen_pad_o => ,
289 mtxerr_pad_o => ,
290 mrx_clk_pad_i => ,
291 mrxd_pad_i => ,
292 mrxdv_pad_i => ,
293 mrxerr_pad_i => ,
294 mcoll_pad_i => ,
295 mcrs_pad_i => ,
296 mdc_pad_o => ,
297 md_pad_i => ,
298 md_pad_o => ,
299 md_padoe_o => ,
300 int_o =>
301 );
302
303 end architecture bla;
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