Update ChipScope coregeneration to coregen as used in ISE Design Suite 10.1
[raggedstone] / dhwk / Makefile
1 PROJECT := dhwk
2 CLEANFILES := dhwk_fifo* fifo_generator_* param.opt icon.vhd icon.vho icon_flist.txt icon_readme.txt icon_xmdf.tcl ila.vhd ila.vho ila_flist.txt ila_readme.txt ila_xmdf.tcl vio.vhd vio.vho vio_flist.txt vio_readme.txt vio_xmdf.tcl
3
4 dhwk_all: ip all
5
6 ip: icon.ngc ila.ngc vio.ngc dhwk_fifo.ngc
7
8 icon.ngc: icon.xco
9 coregen -b $<
10 -rmdir -p tmp/_cg
11
12 ila.ngc: ila.xco
13 coregen -b $<
14 -rmdir -p tmp/_cg
15
16 vio.ngc: vio.xco
17 coregen -b $<
18 -rmdir -p tmp/_cg
19
20 dhwk_fifo.ngc: fifo.xco
21 coregen -b $<
22 -rmdir -p tmp/_cg
23
24 test:
25 grep -q dhwk /proc/modules || (cd driver; ./build; sudo insmod dhwk.ko; sudo mknod -m 666 /dev/dhwk c 42 0)
26 dd if=/dev/urandom of=/tmp/in bs=1024 count=1024
27 (dd if=/dev/dhwk of=/tmp/out bs=1024 count=1024; md5sum /tmp/in /tmp/out)&
28 dd if=/tmp/in of=/dev/dhwk bs=1024 count=1024
29
30 include ../common/Makefile.common
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