1 //////////////////////////////////////////////////////////////////////
3 //// eth_txcounters.v ////
5 //// This file is part of the Ethernet IP core project ////
6 //// http://www.opencores.org/projects/ethmac/ ////
9 //// - Igor Mohor (igorM@opencores.org) ////
10 //// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
11 //// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
13 //// All additional information is avaliable in the Readme.txt ////
16 //////////////////////////////////////////////////////////////////////
18 //// Copyright (C) 2001 Authors ////
20 //// This source file may be used and distributed without ////
21 //// restriction provided that this copyright statement is not ////
22 //// removed from the file and that any derivative work contains ////
23 //// the original copyright notice and the associated disclaimer. ////
25 //// This source file is free software; you can redistribute it ////
26 //// and/or modify it under the terms of the GNU Lesser General ////
27 //// Public License as published by the Free Software Foundation; ////
28 //// either version 2.1 of the License, or (at your option) any ////
29 //// later version. ////
31 //// This source is distributed in the hope that it will be ////
32 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
33 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
34 //// PURPOSE. See the GNU Lesser General Public License for more ////
37 //// You should have received a copy of the GNU Lesser General ////
38 //// Public License along with this source; if not, download it ////
39 //// from http://www.opencores.org/lgpl.shtml ////
41 //////////////////////////////////////////////////////////////////////
43 // CVS Revision History
45 // $Log: eth_txcounters.v,v $
46 // Revision 1.1 2007-03-20 17:50:56 sithglan
49 // Revision 1.6 2005/02/21 11:25:27 igorm
52 // Revision 1.5 2002/04/22 14:54:14 mohor
53 // FCS should not be included in NibbleMinFl.
55 // Revision 1.4 2002/01/23 10:28:16 mohor
56 // Link in the header changed.
58 // Revision 1.3 2001/10/19 08:43:51 mohor
59 // eth_timescale.v changed to timescale.v This is done because of the
60 // simulation of the few cores in a one joined project.
62 // Revision 1.2 2001/09/11 14:17:00 mohor
63 // Few little NCSIM warnings fixed.
65 // Revision 1.1 2001/08/06 14:44:29 mohor
66 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
67 // Include files fixed to contain no path.
68 // File names and module names changed ta have a eth_ prologue in the name.
69 // File eth_timescale.v is used to define timescale
70 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
71 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
72 // and Mdo_OE. The bidirectional signal must be created on the top level. This
73 // is done due to the ASIC tools.
75 // Revision 1.1 2001/07/30 21:23:42 mohor
76 // Directory structure changed. Files checked and joind together.
78 // Revision 1.4 2001/06/27 21:27:45 mohor
81 // Revision 1.2 2001/06/19 10:38:07 mohor
82 // Minor changes in header.
84 // Revision 1.1 2001/06/19 10:27:57 mohor
85 // TxEthMAC initial release.
91 `include "timescale.v"
94 module eth_txcounters (StatePreamble, StateIPG, StateData, StatePAD, StateFCS, StateJam,
95 StateBackOff, StateDefer, StateIdle, StartDefer, StartIPG, StartFCS,
96 StartJam, StartBackoff, TxStartFrm, MTxClk, Reset, MinFL, MaxFL, HugEn,
97 ExDfrEn, PacketFinished_q, DlyCrcEn, StateSFD, ByteCnt, NibCnt,
98 ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt
103 input MTxClk; // Tx clock
104 input Reset; // Reset
105 input StatePreamble; // Preamble state
106 input StateIPG; // IPG state
107 input [1:0] StateData; // Data state
108 input StatePAD; // PAD state
109 input StateFCS; // FCS state
110 input StateJam; // Jam state
111 input StateBackOff; // Backoff state
112 input StateDefer; // Defer state
113 input StateIdle; // Idle state
114 input StateSFD; // SFD state
115 input StartDefer; // Defer state will be activated in next clock
116 input StartIPG; // IPG state will be activated in next clock
117 input StartFCS; // FCS state will be activated in next clock
118 input StartJam; // Jam state will be activated in next clock
119 input StartBackoff; // Backoff state will be activated in next clock
120 input TxStartFrm; // Tx start frame
121 input [15:0] MinFL; // Minimum frame length (in bytes)
122 input [15:0] MaxFL; // Miximum frame length (in bytes)
123 input HugEn; // Pakets bigger then MaxFL enabled
124 input ExDfrEn; // Excessive deferral enabled
125 input PacketFinished_q;
126 input DlyCrcEn; // Delayed CRC enabled
128 output [15:0] ByteCnt; // Byte counter
129 output [15:0] NibCnt; // Nibble counter
130 output ExcessiveDefer; // Excessive Deferral occuring
131 output NibCntEq7; // Nibble counter is equal to 7
132 output NibCntEq15; // Nibble counter is equal to 15
133 output MaxFrame; // Maximum frame occured
134 output NibbleMinFl; // Nibble counter is greater than the minimum frame length
135 output [2:0] DlyCrcCnt; // Delayed CRC Count
137 wire ExcessiveDeferCnt;
139 wire IncrementNibCnt;
141 wire IncrementByteCnt;
150 assign IncrementNibCnt = StateIPG | StatePreamble | (|StateData) | StatePAD
151 | StateFCS | StateJam | StateBackOff | StateDefer & ~ExcessiveDefer & TxStartFrm;
154 assign ResetNibCnt = StateDefer & ExcessiveDefer & ~TxStartFrm | StatePreamble & NibCntEq15
155 | StateJam & NibCntEq7 | StateIdle | StartDefer | StartIPG | StartFCS | StartJam;
158 always @ (posedge MTxClk or posedge Reset)
168 NibCnt <= #Tp NibCnt + 1'b1;
173 assign NibCntEq7 = &NibCnt[2:0];
174 assign NibCntEq15 = &NibCnt[3:0];
176 assign NibbleMinFl = NibCnt >= (((MinFL-3'h4)<<1) -1); // FCS should not be included in NibbleMinFl
178 assign ExcessiveDeferCnt = NibCnt[13:0] == 16'h17b7;
180 assign ExcessiveDefer = NibCnt[13:0] == 16'h17b7 & ~ExDfrEn; // 6071 nibbles
182 assign IncrementByteCnt = StateData[1] & ~ByteCntMax
183 | StateBackOff & (&NibCnt[6:0])
184 | (StatePAD | StateFCS) & NibCnt[0] & ~ByteCntMax;
186 assign ResetByteCnt = StartBackoff | StateIdle & TxStartFrm | PacketFinished_q;
189 // Transmit Byte Counter
190 always @ (posedge MTxClk or posedge Reset)
193 ByteCnt[15:0] <= #Tp 16'h0;
197 ByteCnt[15:0] <= #Tp 16'h0;
200 ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
205 assign MaxFrame = ByteCnt[15:0] == MaxFL[15:0] & ~HugEn;
207 assign ByteCntMax = &ByteCnt[15:0];
210 // Delayed CRC counter
211 always @ (posedge MTxClk or posedge Reset)
214 DlyCrcCnt <= #Tp 3'h0;
217 if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q)
218 DlyCrcCnt <= #Tp 3'h0;
220 if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0])))
221 DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;