1 //////////////////////////////////////////////////////////////////////
3 //// File name "pci_bridge32.v" ////
5 //// This file is part of the "PCI bridge" project ////
6 //// http://www.opencores.org/cores/pci/ ////
9 //// - Miha Dolenc (mihad@opencores.org) ////
10 //// - Tadej Markovic (tadej@opencores.org) ////
12 //// All additional information is avaliable in the README ////
16 //////////////////////////////////////////////////////////////////////
18 //// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
20 //// This source file may be used and distributed without ////
21 //// restriction provided that this copyright statement is not ////
22 //// removed from the file and that any derivative work contains ////
23 //// the original copyright notice and the associated disclaimer. ////
25 //// This source file is free software; you can redistribute it ////
26 //// and/or modify it under the terms of the GNU Lesser General ////
27 //// Public License as published by the Free Software Foundation; ////
28 //// either version 2.1 of the License, or (at your option) any ////
29 //// later version. ////
31 //// This source is distributed in the hope that it will be ////
32 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
33 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
34 //// PURPOSE. See the GNU Lesser General Public License for more ////
37 //// You should have received a copy of the GNU Lesser General ////
38 //// Public License along with this source; if not, download it ////
39 //// from http://www.opencores.org/lgpl.shtml ////
41 //////////////////////////////////////////////////////////////////////
43 // CVS Revision History
45 // $Log: pci_bridge32.v,v $
46 // Revision 1.1 2007-03-20 17:50:56 sithglan
49 // Revision 1.19 2004/09/23 13:48:53 mihad
50 // The control inputs from PCI are now muxed with control outputs
51 // using output enable state for given signal.
53 // Revision 1.18 2004/08/19 15:27:34 mihad
54 // Changed minimum pci image size to 256 bytes because
55 // of some PC system problems with size of IO images.
57 // Revision 1.17 2004/01/24 11:54:18 mihad
58 // Update! SPOCI Implemented!
60 // Revision 1.16 2003/12/19 11:11:30 mihad
61 // Compact PCI Hot Swap support added.
62 // New testcases added.
63 // Specification updated.
64 // Test application changed to support WB B3 cycles.
66 // Revision 1.15 2003/12/10 12:02:54 mihad
67 // The wbs B3 to B2 translation logic had wrong reset wire connected!
69 // Revision 1.14 2003/12/09 09:33:57 simons
70 // Some warning cleanup.
72 // Revision 1.13 2003/10/17 09:11:52 markom
73 // mbist signals updated according to newest convention
75 // Revision 1.12 2003/08/21 20:49:03 tadejm
76 // Added signals for WB Master B3.
78 // Revision 1.11 2003/08/08 16:36:33 tadejm
79 // Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.
81 // Revision 1.10 2003/08/03 18:05:06 mihad
82 // Added limited WISHBONE B3 support for WISHBONE Slave Unit.
83 // Doesn't support full speed bursts yet.
85 // Revision 1.9 2003/01/27 16:49:31 mihad
86 // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
88 // Revision 1.8 2002/10/21 13:04:33 mihad
89 // Changed BIST signal names etc..
91 // Revision 1.7 2002/10/18 03:36:37 tadejm
92 // Changed wrong signal name mbist_sen into mbist_ctrl_i.
94 // Revision 1.6 2002/10/17 22:51:50 tadejm
95 // Changed BIST signals for RAMs.
97 // Revision 1.5 2002/10/11 10:09:01 mihad
98 // Added additional testcase and changed rst name in BIST to trst
100 // Revision 1.4 2002/10/08 17:17:05 mihad
101 // Added BIST signals for RAMs.
103 // Revision 1.3 2002/02/01 15:25:12 mihad
104 // Repaired a few bugs, updated specification, added test bench files and design document
106 // Revision 1.2 2001/10/05 08:14:28 mihad
107 // Updated all files with inclusion of timescale file for simulation purposes.
109 // Revision 1.1.1.1 2001/10/02 15:33:46 mihad
110 // New project directory structure
114 `include "pci_constants.v"
116 // synopsys translate_off
117 `include "timescale.v"
118 // synopsys translate_on
120 // this is top level module of pci bridge core
121 // it instantiates and connects other lower level modules
122 // check polarity of PCI output enables in file out_reg.v and change it according to IO interface specification
126 // WISHBONE system signals
133 // WISHBONE slave interface
157 // WISHBONE master interface
171 // pci interface - system pins
212 // data transfer pins
219 // parity generation and checking pins
234 // debug chain signals
235 mbist_si_i, // bist scan serial in
236 mbist_so_o, // bist scan serial out
237 mbist_ctrl_i // bist chain shift control
240 `ifdef PCI_CPCI_HS_IMPLEMENT
242 // Compact PCI Hot Swap signals
243 pci_cpci_hs_enum_o , // ENUM# output with output enable (open drain)
244 pci_cpci_hs_enum_oe_o , // ENUM# enum output enable
245 pci_cpci_hs_led_o , // LED output with output enable (open drain)
246 pci_cpci_hs_led_oe_o , // LED output enable
247 pci_cpci_hs_es_i // ejector switch state indicator input
252 // Serial power on configuration interface
264 parameter pci_ba0_width = `PCI_NUM_OF_DEC_ADDR_LINES ;
266 parameter pci_ba0_width = 20 ;
271 parameter pci_ba0_width = 20 ;
274 parameter pci_ba1_5_width = `PCI_NUM_OF_DEC_ADDR_LINES ;
276 // WISHBONE system signals
283 // WISHBONE slave interface
284 input [31:0] wbs_adr_i ;
285 input [31:0] wbs_dat_i ;
286 output [31:0] wbs_dat_o ;
287 input [3:0] wbs_sel_i ;
294 input [2:0] wbs_cti_i ;
295 input [1:0] wbs_bte_i ;
307 // WISHBONE master interface
308 output [31:0] wbm_adr_o ;
309 input [31:0] wbm_dat_i ;
310 output [31:0] wbm_dat_o ;
311 output [3:0] wbm_sel_o ;
315 output [2:0] wbm_cti_o ;
316 output [1:0] wbm_bte_o ;
321 // pci interface - system pins
325 output pci_rst_oe_o ;
329 output pci_inta_oe_o ;
333 output pci_req_oe_o ;
340 output pci_frame_oe_o ;
341 output pci_irdy_oe_o ;
342 output pci_devsel_oe_o ;
343 output pci_trdy_oe_o ;
344 output pci_stop_oe_o ;
345 output [31:0] pci_ad_oe_o ;
346 output [3:0] pci_cbe_oe_o ;
354 output pci_devsel_o ;
362 // data transfer pins
363 input [31:0] pci_ad_i ;
364 output [31:0] pci_ad_o ;
366 input [3:0] pci_cbe_i ;
367 output [3:0] pci_cbe_o ;
369 // parity generation and checking pins
372 output pci_par_oe_o ;
376 output pci_perr_oe_o ;
380 output pci_serr_oe_o ;
383 /*-----------------------------------------------------
384 BIST debug chain port signals
385 -----------------------------------------------------*/
386 input mbist_si_i; // bist scan serial in
387 output mbist_so_o; // bist scan serial out
388 input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
391 `ifdef PCI_CPCI_HS_IMPLEMENT
392 // Compact PCI Hot Swap signals
393 output pci_cpci_hs_enum_o ; // ENUM# output with output enable (open drain)
394 output pci_cpci_hs_enum_oe_o ; // ENUM# enum output enable
395 output pci_cpci_hs_led_o ; // LED output with output enable (open drain)
396 output pci_cpci_hs_led_oe_o ; // LED output enable
397 input pci_cpci_hs_es_i ; // ejector switch state indicator input
399 assign pci_cpci_hs_enum_o = 1'b0 ;
400 assign pci_cpci_hs_led_o = 1'b0 ;
405 output spoci_scl_oe_o ;
408 output spoci_sda_oe_o ;
410 assign spoci_scl_o = 1'b0 ;
411 assign spoci_sda_o = 1'b0 ;
414 // declare clock and reset wires
415 wire pci_clk = pci_clk_i ;
416 wire wb_clk = wb_clk_i ;
417 wire reset ; // assigned at pci bridge reset and interrupt logic
419 /*=========================================================================================================
420 First comes definition of all modules' outputs, so they can be assigned to any other module's input later
421 in the file, when module is instantiated
422 =========================================================================================================*/
423 // PCI BRIDGE RESET AND INTERRUPT LOGIC OUTPUTS
424 wire pci_reso_reset ;
425 wire pci_reso_pci_rstn_out ;
426 wire pci_reso_pci_rstn_en_out ;
427 wire pci_reso_rst_o ;
428 wire pci_into_pci_intan_out ;
429 wire pci_into_pci_intan_en_out ;
430 wire pci_into_int_o ;
431 wire pci_into_conf_isr_int_prop_out ;
433 // assign pci bridge reset interrupt logic outputs to top outputs where possible
434 assign reset = pci_reso_reset ;
435 assign pci_rst_o = pci_reso_pci_rstn_out ;
436 assign pci_rst_oe_o = pci_reso_pci_rstn_en_out ;
437 assign wb_rst_o = pci_reso_rst_o ;
438 assign pci_inta_o = pci_into_pci_intan_out ;
439 assign pci_inta_oe_o = pci_into_pci_intan_en_out ;
440 assign wb_int_o = pci_into_int_o ;
442 // WISHBONE SLAVE UNIT OUTPUTS
443 wire [31:0] wbu_sdata_out ;
447 wire wbu_pciif_req_out ;
448 wire wbu_pciif_frame_out ;
449 wire wbu_pciif_frame_en_out ;
450 wire wbu_pciif_irdy_out ;
451 wire wbu_pciif_irdy_en_out ;
452 wire [31:0] wbu_pciif_ad_out ;
453 wire wbu_pciif_ad_en_out ;
454 wire [3:0] wbu_pciif_cbe_out ;
455 wire wbu_pciif_cbe_en_out ;
456 wire [31:0] wbu_err_addr_out ;
457 wire [3:0] wbu_err_bc_out ;
458 wire wbu_err_signal_out ;
459 wire wbu_err_source_out ;
460 wire wbu_err_rty_exp_out ;
461 wire wbu_tabort_rec_out ;
462 wire wbu_mabort_rec_out ;
463 wire [11:0] wbu_conf_offset_out ;
464 wire wbu_conf_renable_out ;
465 wire wbu_conf_wenable_out ;
466 wire [3:0] wbu_conf_be_out ;
467 wire [31:0] wbu_conf_data_out ;
468 wire wbu_del_read_comp_pending_out ;
469 wire wbu_wbw_fifo_empty_out ;
470 wire wbu_ad_load_out ;
471 wire wbu_ad_load_on_transfer_out ;
472 wire wbu_pciif_frame_load_out ;
474 // PCI TARGET UNIT OUTPUTS
475 wire [31:0] pciu_adr_out ;
476 wire [31:0] pciu_mdata_out ;
480 wire [2:0] pciu_cti_out ;
481 wire [1:0] pciu_bte_out ;
482 wire [3:0] pciu_sel_out ;
483 wire pciu_pciif_trdy_out ;
484 wire pciu_pciif_stop_out ;
485 wire pciu_pciif_devsel_out ;
486 wire pciu_pciif_trdy_en_out ;
487 wire pciu_pciif_stop_en_out ;
488 wire pciu_pciif_devsel_en_out ;
489 wire pciu_ad_load_out ;
490 wire pciu_ad_load_on_transfer_out ;
491 wire [31:0] pciu_pciif_ad_out ;
492 wire pciu_pciif_ad_en_out ;
493 wire pciu_pciif_tabort_set_out ;
494 wire [31:0] pciu_err_addr_out ;
495 wire [3:0] pciu_err_bc_out ;
496 wire [31:0] pciu_err_data_out ;
497 wire [3:0] pciu_err_be_out ;
498 wire pciu_err_signal_out ;
499 wire pciu_err_source_out ;
500 wire pciu_err_rty_exp_out ;
501 wire [11:0] pciu_conf_offset_out ;
502 wire pciu_conf_renable_out ;
503 wire pciu_conf_wenable_out ;
504 wire [3:0] pciu_conf_be_out ;
505 wire [31:0] pciu_conf_data_out ;
506 wire pciu_pci_drcomp_pending_out ;
507 wire pciu_pciw_fifo_empty_out ;
509 // assign pci target unit's outputs to top outputs where possible
510 assign wbm_adr_o = pciu_adr_out ;
511 assign wbm_dat_o = pciu_mdata_out ;
512 assign wbm_cyc_o = pciu_cyc_out ;
513 assign wbm_stb_o = pciu_stb_out ;
514 assign wbm_we_o = pciu_we_out ;
515 assign wbm_cti_o = pciu_cti_out ;
516 assign wbm_bte_o = pciu_bte_out ;
517 assign wbm_sel_o = pciu_sel_out ;
519 // CONFIGURATION SPACE OUTPUTS
520 wire [31:0] conf_w_data_out ;
521 wire [31:0] conf_r_data_out ;
522 wire conf_serr_enable_out ;
523 wire conf_perr_response_out ;
524 wire conf_pci_master_enable_out ;
525 wire conf_mem_space_enable_out ;
526 wire conf_io_space_enable_out ;
527 wire [7:0] conf_cache_line_size_to_pci_out ;
528 wire [7:0] conf_cache_line_size_to_wb_out ;
529 wire conf_cache_lsize_not_zero_to_wb_out ;
530 wire [7:0] conf_latency_tim_out ;
532 wire [pci_ba0_width - 1:0] conf_pci_ba0_out ;
533 wire [pci_ba1_5_width - 1:0] conf_pci_ba1_out ;
534 wire [pci_ba1_5_width - 1:0] conf_pci_ba2_out ;
535 wire [pci_ba1_5_width - 1:0] conf_pci_ba3_out ;
536 wire [pci_ba1_5_width - 1:0] conf_pci_ba4_out ;
537 wire [pci_ba1_5_width - 1:0] conf_pci_ba5_out ;
538 wire [pci_ba1_5_width - 1:0] conf_pci_ta0_out ;
539 wire [pci_ba1_5_width - 1:0] conf_pci_ta1_out ;
540 wire [pci_ba1_5_width - 1:0] conf_pci_ta2_out ;
541 wire [pci_ba1_5_width - 1:0] conf_pci_ta3_out ;
542 wire [pci_ba1_5_width - 1:0] conf_pci_ta4_out ;
543 wire [pci_ba1_5_width - 1:0] conf_pci_ta5_out ;
544 wire [pci_ba1_5_width - 1:0] conf_pci_am0_out ;
545 wire [pci_ba1_5_width - 1:0] conf_pci_am1_out ;
546 wire [pci_ba1_5_width - 1:0] conf_pci_am2_out ;
547 wire [pci_ba1_5_width - 1:0] conf_pci_am3_out ;
548 wire [pci_ba1_5_width - 1:0] conf_pci_am4_out ;
549 wire [pci_ba1_5_width - 1:0] conf_pci_am5_out ;
551 wire conf_pci_mem_io0_out ;
552 wire conf_pci_mem_io1_out ;
553 wire conf_pci_mem_io2_out ;
554 wire conf_pci_mem_io3_out ;
555 wire conf_pci_mem_io4_out ;
556 wire conf_pci_mem_io5_out ;
558 wire [1:0] conf_pci_img_ctrl0_out ;
559 wire [1:0] conf_pci_img_ctrl1_out ;
560 wire [1:0] conf_pci_img_ctrl2_out ;
561 wire [1:0] conf_pci_img_ctrl3_out ;
562 wire [1:0] conf_pci_img_ctrl4_out ;
563 wire [1:0] conf_pci_img_ctrl5_out ;
565 wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba0_out ;
566 wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba1_out ;
567 wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba2_out ;
568 wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba3_out ;
569 wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba4_out ;
570 wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ba5_out ;
572 wire conf_wb_mem_io0_out ;
573 wire conf_wb_mem_io1_out ;
574 wire conf_wb_mem_io2_out ;
575 wire conf_wb_mem_io3_out ;
576 wire conf_wb_mem_io4_out ;
577 wire conf_wb_mem_io5_out ;
579 wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am0_out ;
580 wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am1_out ;
581 wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am2_out ;
582 wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am3_out ;
583 wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am4_out ;
584 wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_am5_out ;
585 wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta0_out ;
586 wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta1_out ;
587 wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta2_out ;
588 wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta3_out ;
589 wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta4_out ;
590 wire [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)] conf_wb_ta5_out ;
591 wire [2:0] conf_wb_img_ctrl0_out ;
592 wire [2:0] conf_wb_img_ctrl1_out ;
593 wire [2:0] conf_wb_img_ctrl2_out ;
594 wire [2:0] conf_wb_img_ctrl3_out ;
595 wire [2:0] conf_wb_img_ctrl4_out ;
596 wire [2:0] conf_wb_img_ctrl5_out ;
597 wire [23:0] conf_ccyc_addr_out ;
598 wire conf_soft_res_out ;
600 wire conf_wb_init_complete_out ;
601 wire conf_pci_init_complete_out ;
603 // PCI IO MUX OUTPUTS
604 wire pci_mux_frame_out ;
605 wire pci_mux_irdy_out ;
606 wire pci_mux_devsel_out ;
607 wire pci_mux_trdy_out ;
608 wire pci_mux_stop_out ;
609 wire [3:0] pci_mux_cbe_out ;
610 wire [31:0] pci_mux_ad_out ;
611 wire pci_mux_ad_load_out ;
613 wire [31:0] pci_mux_ad_en_out ;
614 wire pci_mux_ad_en_unregistered_out ;
615 wire pci_mux_frame_en_out ;
616 wire pci_mux_irdy_en_out ;
617 wire pci_mux_devsel_en_out ;
618 wire pci_mux_trdy_en_out ;
619 wire pci_mux_stop_en_out ;
620 wire [3:0] pci_mux_cbe_en_out ;
622 wire pci_mux_par_out ;
623 wire pci_mux_par_en_out ;
624 wire pci_mux_perr_out ;
625 wire pci_mux_perr_en_out ;
626 wire pci_mux_serr_out ;
627 wire pci_mux_serr_en_out ;
629 wire pci_mux_req_out ;
630 wire pci_mux_req_en_out ;
632 // assign outputs to top level outputs
634 assign pci_ad_oe_o = pci_mux_ad_en_out ;
635 assign pci_frame_oe_o = pci_mux_frame_en_out ;
636 assign pci_irdy_oe_o = pci_mux_irdy_en_out ;
637 assign pci_cbe_oe_o = pci_mux_cbe_en_out ;
639 assign pci_par_o = pci_mux_par_out ;
640 assign pci_par_oe_o = pci_mux_par_en_out ;
641 assign pci_perr_o = pci_mux_perr_out ;
642 assign pci_perr_oe_o = pci_mux_perr_en_out ;
643 assign pci_serr_o = pci_mux_serr_out ;
644 assign pci_serr_oe_o = pci_mux_serr_en_out ;
646 assign pci_req_o = pci_mux_req_out ;
647 assign pci_req_oe_o = pci_mux_req_en_out ;
649 assign pci_trdy_oe_o = pci_mux_trdy_en_out ;
650 assign pci_devsel_oe_o = pci_mux_devsel_en_out ;
651 assign pci_stop_oe_o = pci_mux_stop_en_out ;
652 assign pci_trdy_o = pci_mux_trdy_out ;
653 assign pci_devsel_o = pci_mux_devsel_out ;
654 assign pci_stop_o = pci_mux_stop_out ;
656 assign pci_ad_o = pci_mux_ad_out ;
657 assign pci_frame_o = pci_mux_frame_out ;
658 assign pci_irdy_o = pci_mux_irdy_out ;
659 assign pci_cbe_o = pci_mux_cbe_out ;
661 // duplicate output register's outputs
662 wire out_bckp_frame_out ;
663 wire out_bckp_irdy_out ;
664 wire out_bckp_devsel_out ;
665 wire out_bckp_trdy_out ;
666 wire out_bckp_stop_out ;
667 wire [3:0] out_bckp_cbe_out ;
668 wire out_bckp_cbe_en_out ;
669 wire [31:0] out_bckp_ad_out ;
670 wire out_bckp_ad_en_out ;
671 wire out_bckp_irdy_en_out ;
672 wire out_bckp_frame_en_out ;
673 wire out_bckp_tar_ad_en_out ;
674 wire out_bckp_mas_ad_en_out ;
675 wire out_bckp_trdy_en_out ;
677 wire out_bckp_par_out ;
678 wire out_bckp_par_en_out ;
679 wire out_bckp_perr_out ;
680 wire out_bckp_perr_en_out ;
681 wire out_bckp_serr_out ;
682 wire out_bckp_serr_en_out ;
684 wire int_pci_frame = out_bckp_frame_en_out ? out_bckp_frame_out : pci_frame_i ;
685 wire int_pci_irdy = out_bckp_irdy_en_out ? out_bckp_irdy_out : pci_irdy_i ;
686 wire int_pci_devsel = out_bckp_trdy_en_out ? out_bckp_devsel_out : pci_devsel_i ;
687 wire int_pci_trdy = out_bckp_trdy_en_out ? out_bckp_trdy_out : pci_trdy_i ;
688 wire int_pci_stop = out_bckp_trdy_en_out ? out_bckp_stop_out : pci_stop_i ;
689 wire [ 3: 0] int_pci_cbe = out_bckp_cbe_en_out ? out_bckp_cbe_out : pci_cbe_i ;
690 wire int_pci_par = out_bckp_par_en_out ? out_bckp_par_out : pci_par_i ;
691 wire int_pci_perr = out_bckp_perr_en_out ? out_bckp_perr_out : pci_perr_i ;
692 // PARITY CHECKER OUTPUTS
693 wire parchk_pci_par_out ;
694 wire parchk_pci_par_en_out ;
695 wire parchk_pci_perr_out ;
696 wire parchk_pci_perr_en_out ;
697 wire parchk_pci_serr_out ;
698 wire parchk_pci_serr_en_out ;
699 wire parchk_par_err_detect_out ;
700 wire parchk_perr_mas_detect_out ;
701 wire parchk_sig_serr_out ;
703 // input register outputs
704 wire in_reg_gnt_out ;
705 wire in_reg_frame_out ;
706 wire in_reg_irdy_out ;
707 wire in_reg_trdy_out ;
708 wire in_reg_stop_out ;
709 wire in_reg_devsel_out ;
710 wire in_reg_idsel_out ;
711 wire [31:0] in_reg_ad_out ;
712 wire [3:0] in_reg_cbe_out ;
714 /*=========================================================================================================
715 Now comes definition of all modules' and their appropriate inputs
716 =========================================================================================================*/
717 // PCI BRIDGE RESET AND INTERRUPT LOGIC INPUTS
718 wire pci_resi_rst_i = wb_rst_i ;
719 wire pci_resi_pci_rstn_in = pci_rst_i ;
720 wire pci_resi_conf_soft_res_in = conf_soft_res_out ;
721 wire pci_inti_pci_intan_in = pci_inta_i ;
722 wire pci_inti_conf_int_in = conf_int_out ;
723 wire pci_inti_int_i = wb_int_i ;
724 wire pci_into_init_complete_in = conf_pci_init_complete_out ;
726 pci_rst_int pci_resets_and_interrupts
729 .rst_i (pci_resi_rst_i),
730 .pci_rstn_in (pci_resi_pci_rstn_in),
731 .conf_soft_res_in (pci_resi_conf_soft_res_in),
732 .reset (pci_reso_reset),
733 .pci_rstn_out (pci_reso_pci_rstn_out),
734 .pci_rstn_en_out (pci_reso_pci_rstn_en_out),
735 .rst_o (pci_reso_rst_o),
736 .pci_intan_in (pci_inti_pci_intan_in),
737 .conf_int_in (pci_inti_conf_int_in),
738 .int_i (pci_inti_int_i),
739 .pci_intan_out (pci_into_pci_intan_out),
740 .pci_intan_en_out (pci_into_pci_intan_en_out),
741 .int_o (pci_into_int_o),
742 .conf_isr_int_prop_out (pci_into_conf_isr_int_prop_out),
743 .init_complete_in (pci_into_init_complete_in)
749 wire wbs_wbb3_2_wbb2_cyc_o ;
750 wire wbs_wbb3_2_wbb2_stb_o ;
751 wire [31:0] wbs_wbb3_2_wbb2_adr_o ;
752 wire [31:0] wbs_wbb3_2_wbb2_dat_i_o ;
753 wire [31:0] wbs_wbb3_2_wbb2_dat_o_o ;
754 wire wbs_wbb3_2_wbb2_we_o ;
755 wire [ 3:0] wbs_wbb3_2_wbb2_sel_o ;
756 wire wbs_wbb3_2_wbb2_ack_o ;
757 wire wbs_wbb3_2_wbb2_err_o ;
758 wire wbs_wbb3_2_wbb2_rty_o ;
759 wire wbs_wbb3_2_wbb2_cab_o ;
761 // assign wishbone slave unit's outputs to top outputs where possible
762 assign wbs_dat_o = wbs_wbb3_2_wbb2_dat_o_o ;
763 assign wbs_ack_o = wbs_wbb3_2_wbb2_ack_o ;
764 assign wbs_rty_o = wbs_wbb3_2_wbb2_rty_o ;
765 assign wbs_err_o = wbs_wbb3_2_wbb2_err_o ;
767 wire wbs_wbb3_2_wbb2_cyc_i = wbs_cyc_i ;
768 wire wbs_wbb3_2_wbb2_stb_i = wbs_stb_i ;
769 wire wbs_wbb3_2_wbb2_we_i = wbs_we_i ;
770 wire wbs_wbb3_2_wbb2_ack_i = wbu_ack_out ;
771 wire wbs_wbb3_2_wbb2_err_i = wbu_err_out ;
772 wire wbs_wbb3_2_wbb2_rty_i = wbu_rty_out ;
773 wire [31:0] wbs_wbb3_2_wbb2_adr_i = wbs_adr_i ;
774 wire [ 3:0] wbs_wbb3_2_wbb2_sel_i = wbs_sel_i ;
775 wire [31:0] wbs_wbb3_2_wbb2_dat_i_i = wbs_dat_i ;
776 wire [31:0] wbs_wbb3_2_wbb2_dat_o_i = wbu_sdata_out ;
777 wire [ 2:0] wbs_wbb3_2_wbb2_cti_i = wbs_cti_i ;
778 wire [ 1:0] wbs_wbb3_2_wbb2_bte_i = wbs_bte_i ;
780 pci_wbs_wbb3_2_wbb2 i_pci_wbs_wbb3_2_wbb2
782 .wb_clk_i ( wb_clk_i ) ,
783 .wb_rst_i ( reset ) ,
785 .wbs_cyc_i ( wbs_wbb3_2_wbb2_cyc_i ) ,
786 .wbs_cyc_o ( wbs_wbb3_2_wbb2_cyc_o ) ,
787 .wbs_stb_i ( wbs_wbb3_2_wbb2_stb_i ) ,
788 .wbs_stb_o ( wbs_wbb3_2_wbb2_stb_o ) ,
789 .wbs_adr_i ( wbs_wbb3_2_wbb2_adr_i ) ,
790 .wbs_adr_o ( wbs_wbb3_2_wbb2_adr_o ) ,
791 .wbs_dat_i_i ( wbs_wbb3_2_wbb2_dat_i_i ) ,
792 .wbs_dat_i_o ( wbs_wbb3_2_wbb2_dat_i_o ) ,
793 .wbs_dat_o_i ( wbs_wbb3_2_wbb2_dat_o_i ) ,
794 .wbs_dat_o_o ( wbs_wbb3_2_wbb2_dat_o_o ) ,
795 .wbs_we_i ( wbs_wbb3_2_wbb2_we_i ) ,
796 .wbs_we_o ( wbs_wbb3_2_wbb2_we_o ) ,
797 .wbs_sel_i ( wbs_wbb3_2_wbb2_sel_i ) ,
798 .wbs_sel_o ( wbs_wbb3_2_wbb2_sel_o ) ,
799 .wbs_ack_i ( wbs_wbb3_2_wbb2_ack_i ) ,
800 .wbs_ack_o ( wbs_wbb3_2_wbb2_ack_o ) ,
801 .wbs_err_i ( wbs_wbb3_2_wbb2_err_i ) ,
802 .wbs_err_o ( wbs_wbb3_2_wbb2_err_o ) ,
803 .wbs_rty_i ( wbs_wbb3_2_wbb2_rty_i ) ,
804 .wbs_rty_o ( wbs_wbb3_2_wbb2_rty_o ) ,
805 .wbs_cti_i ( wbs_wbb3_2_wbb2_cti_i ) ,
806 .wbs_bte_i ( wbs_wbb3_2_wbb2_bte_i ) ,
807 .wbs_cab_o ( wbs_wbb3_2_wbb2_cab_o ) ,
808 .wb_init_complete_i ( conf_wb_init_complete_out )
811 // WISHBONE SLAVE UNIT INPUTS
812 wire [31:0] wbu_addr_in = wbs_wbb3_2_wbb2_adr_o ;
813 wire [31:0] wbu_sdata_in = wbs_wbb3_2_wbb2_dat_i_o ;
814 wire wbu_cyc_in = wbs_wbb3_2_wbb2_cyc_o ;
815 wire wbu_stb_in = wbs_wbb3_2_wbb2_stb_o ;
816 wire wbu_we_in = wbs_wbb3_2_wbb2_we_o ;
817 wire [3:0] wbu_sel_in = wbs_wbb3_2_wbb2_sel_o ;
818 wire wbu_cab_in = wbs_wbb3_2_wbb2_cab_o ;
822 // WISHBONE SLAVE UNIT INPUTS
823 wire [31:0] wbu_addr_in = wbs_adr_i ;
824 wire [31:0] wbu_sdata_in = wbs_dat_i ;
825 wire wbu_cyc_in = wbs_cyc_i ;
826 wire wbu_stb_in = wbs_stb_i ;
827 wire wbu_we_in = wbs_we_i ;
828 wire [3:0] wbu_sel_in = wbs_sel_i ;
829 wire wbu_cab_in = wbs_cab_i ;
831 // assign wishbone slave unit's outputs to top outputs where possible
832 assign wbs_dat_o = wbu_sdata_out ;
833 assign wbs_ack_o = wbu_ack_out ;
834 assign wbs_rty_o = wbu_rty_out ;
835 assign wbs_err_o = wbu_err_out ;
839 wire [5:0] wbu_map_in = {
848 wire [5:0] wbu_pref_en_in = {
849 conf_wb_img_ctrl5_out[1],
850 conf_wb_img_ctrl4_out[1],
851 conf_wb_img_ctrl3_out[1],
852 conf_wb_img_ctrl2_out[1],
853 conf_wb_img_ctrl1_out[1],
854 conf_wb_img_ctrl0_out[1]
856 wire [5:0] wbu_mrl_en_in = {
857 conf_wb_img_ctrl5_out[0],
858 conf_wb_img_ctrl4_out[0],
859 conf_wb_img_ctrl3_out[0],
860 conf_wb_img_ctrl2_out[0],
861 conf_wb_img_ctrl1_out[0],
862 conf_wb_img_ctrl0_out[0]
865 wire [5:0] wbu_at_en_in = {
866 conf_wb_img_ctrl5_out[2],
867 conf_wb_img_ctrl4_out[2],
868 conf_wb_img_ctrl3_out[2],
869 conf_wb_img_ctrl2_out[2],
870 conf_wb_img_ctrl1_out[2],
871 conf_wb_img_ctrl0_out[2]
874 wire wbu_pci_drcomp_pending_in = pciu_pci_drcomp_pending_out ;
875 wire wbu_pciw_empty_in = pciu_pciw_fifo_empty_out ;
878 wire [31:0] wbu_conf_data_in = conf_w_data_out ;
881 wire [31:0] wbu_conf_data_in = conf_r_data_out ;
885 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar0_in = conf_wb_ba0_out ;
886 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar1_in = conf_wb_ba1_out ;
887 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar2_in = conf_wb_ba2_out ;
888 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar3_in = conf_wb_ba3_out ;
889 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar4_in = conf_wb_ba4_out ;
890 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_bar5_in = conf_wb_ba5_out ;
891 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am0_in = conf_wb_am0_out ;
892 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am1_in = conf_wb_am1_out ;
893 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am2_in = conf_wb_am2_out ;
894 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am3_in = conf_wb_am3_out ;
895 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am4_in = conf_wb_am4_out ;
896 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_am5_in = conf_wb_am5_out ;
897 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta0_in = conf_wb_ta0_out ;
898 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta1_in = conf_wb_ta1_out ;
899 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta2_in = conf_wb_ta2_out ;
900 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta3_in = conf_wb_ta3_out ;
901 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta4_in = conf_wb_ta4_out ;
902 wire [(`WB_NUM_OF_DEC_ADDR_LINES - 1):0] wbu_ta5_in = conf_wb_ta5_out ;
904 wire [23:0] wbu_ccyc_addr_in = conf_ccyc_addr_out ;
905 wire wbu_master_enable_in = conf_pci_master_enable_out ;
906 wire wbu_cache_line_size_not_zero = conf_cache_lsize_not_zero_to_wb_out ;
907 wire [7:0] wbu_cache_line_size_in = conf_cache_line_size_to_pci_out ;
909 wire wbu_pciif_gnt_in = pci_gnt_i ;
910 wire wbu_pciif_frame_in = in_reg_frame_out ;
911 wire wbu_pciif_irdy_in = in_reg_irdy_out ;
912 wire wbu_pciif_trdy_in = int_pci_trdy ;
913 wire wbu_pciif_stop_in = int_pci_stop ;
914 wire wbu_pciif_devsel_in = int_pci_devsel ;
915 wire [31:0] wbu_pciif_ad_reg_in = in_reg_ad_out ;
916 wire wbu_pciif_trdy_reg_in = in_reg_trdy_out ;
917 wire wbu_pciif_stop_reg_in = in_reg_stop_out ;
918 wire wbu_pciif_devsel_reg_in = in_reg_devsel_out ;
921 wire [7:0] wbu_latency_tim_val_in = conf_latency_tim_out ;
923 wire wbu_pciif_frame_en_in = out_bckp_frame_en_out ;
924 wire wbu_pciif_frame_out_in = out_bckp_frame_out ;
925 wire wbu_wb_init_complete_in = conf_wb_init_complete_out ;
927 pci_wb_slave_unit wishbone_slave_unit
930 .wb_clock_in (wb_clk),
931 .pci_clock_in (pci_clk),
932 .ADDR_I (wbu_addr_in),
933 .SDATA_I (wbu_sdata_in),
934 .SDATA_O (wbu_sdata_out),
939 .ACK_O (wbu_ack_out),
940 .RTY_O (wbu_rty_out),
941 .ERR_O (wbu_err_out),
943 .wbu_map_in (wbu_map_in),
944 .wbu_pref_en_in (wbu_pref_en_in),
945 .wbu_mrl_en_in (wbu_mrl_en_in),
946 .wbu_pci_drcomp_pending_in (wbu_pci_drcomp_pending_in),
947 .wbu_conf_data_in (wbu_conf_data_in),
948 .wbu_pciw_empty_in (wbu_pciw_empty_in),
949 .wbu_bar0_in (wbu_bar0_in),
950 .wbu_bar1_in (wbu_bar1_in),
951 .wbu_bar2_in (wbu_bar2_in),
952 .wbu_bar3_in (wbu_bar3_in),
953 .wbu_bar4_in (wbu_bar4_in),
954 .wbu_bar5_in (wbu_bar5_in),
955 .wbu_am0_in (wbu_am0_in),
956 .wbu_am1_in (wbu_am1_in),
957 .wbu_am2_in (wbu_am2_in),
958 .wbu_am3_in (wbu_am3_in),
959 .wbu_am4_in (wbu_am4_in),
960 .wbu_am5_in (wbu_am5_in),
961 .wbu_ta0_in (wbu_ta0_in),
962 .wbu_ta1_in (wbu_ta1_in),
963 .wbu_ta2_in (wbu_ta2_in),
964 .wbu_ta3_in (wbu_ta3_in),
965 .wbu_ta4_in (wbu_ta4_in),
966 .wbu_ta5_in (wbu_ta5_in),
967 .wbu_at_en_in (wbu_at_en_in),
968 .wbu_ccyc_addr_in (wbu_ccyc_addr_in),
969 .wbu_master_enable_in (wbu_master_enable_in),
970 .wb_init_complete_in (wbu_wb_init_complete_in),
971 .wbu_cache_line_size_not_zero (wbu_cache_line_size_not_zero),
972 .wbu_cache_line_size_in (wbu_cache_line_size_in),
973 .wbu_pciif_gnt_in (wbu_pciif_gnt_in),
974 .wbu_pciif_frame_in (wbu_pciif_frame_in),
975 .wbu_pciif_frame_en_in (wbu_pciif_frame_en_in),
976 .wbu_pciif_frame_out_in (wbu_pciif_frame_out_in),
977 .wbu_pciif_irdy_in (wbu_pciif_irdy_in),
978 .wbu_pciif_trdy_in (wbu_pciif_trdy_in),
979 .wbu_pciif_stop_in (wbu_pciif_stop_in),
980 .wbu_pciif_devsel_in (wbu_pciif_devsel_in),
981 .wbu_pciif_ad_reg_in (wbu_pciif_ad_reg_in),
982 .wbu_pciif_req_out (wbu_pciif_req_out),
983 .wbu_pciif_frame_out (wbu_pciif_frame_out),
984 .wbu_pciif_frame_en_out (wbu_pciif_frame_en_out),
985 .wbu_pciif_frame_load_out (wbu_pciif_frame_load_out),
986 .wbu_pciif_irdy_out (wbu_pciif_irdy_out),
987 .wbu_pciif_irdy_en_out (wbu_pciif_irdy_en_out),
988 .wbu_pciif_ad_out (wbu_pciif_ad_out),
989 .wbu_pciif_ad_en_out (wbu_pciif_ad_en_out),
990 .wbu_pciif_cbe_out (wbu_pciif_cbe_out),
991 .wbu_pciif_cbe_en_out (wbu_pciif_cbe_en_out),
992 .wbu_err_addr_out (wbu_err_addr_out),
993 .wbu_err_bc_out (wbu_err_bc_out),
994 .wbu_err_signal_out (wbu_err_signal_out),
995 .wbu_err_source_out (wbu_err_source_out),
996 .wbu_err_rty_exp_out (wbu_err_rty_exp_out),
997 .wbu_tabort_rec_out (wbu_tabort_rec_out),
998 .wbu_mabort_rec_out (wbu_mabort_rec_out),
999 .wbu_conf_offset_out (wbu_conf_offset_out),
1000 .wbu_conf_renable_out (wbu_conf_renable_out),
1001 .wbu_conf_wenable_out (wbu_conf_wenable_out),
1002 .wbu_conf_be_out (wbu_conf_be_out),
1003 .wbu_conf_data_out (wbu_conf_data_out),
1004 .wbu_del_read_comp_pending_out (wbu_del_read_comp_pending_out),
1005 .wbu_wbw_fifo_empty_out (wbu_wbw_fifo_empty_out),
1006 .wbu_latency_tim_val_in (wbu_latency_tim_val_in),
1007 .wbu_ad_load_out (wbu_ad_load_out),
1008 .wbu_ad_load_on_transfer_out (wbu_ad_load_on_transfer_out),
1009 .wbu_pciif_trdy_reg_in (wbu_pciif_trdy_reg_in),
1010 .wbu_pciif_stop_reg_in (wbu_pciif_stop_reg_in),
1011 .wbu_pciif_devsel_reg_in (wbu_pciif_devsel_reg_in)
1015 .mbist_si_i (mbist_si_i),
1016 .mbist_so_o (mbist_so_o_internal),
1017 .mbist_ctrl_i (mbist_ctrl_i)
1021 // PCI TARGET UNIT INPUTS
1022 wire [31:0] pciu_mdata_in = wbm_dat_i ;
1023 wire pciu_ack_in = wbm_ack_i ;
1024 wire pciu_rty_in = wbm_rty_i ;
1025 wire pciu_err_in = wbm_err_i ;
1027 wire [5:0] pciu_map_in = {
1028 conf_pci_mem_io5_out,
1029 conf_pci_mem_io4_out,
1030 conf_pci_mem_io3_out,
1031 conf_pci_mem_io2_out,
1032 conf_pci_mem_io1_out,
1033 conf_pci_mem_io0_out
1036 wire [5:0] pciu_pref_en_in = {
1037 conf_pci_img_ctrl5_out[0],
1038 conf_pci_img_ctrl4_out[0],
1039 conf_pci_img_ctrl3_out[0],
1040 conf_pci_img_ctrl2_out[0],
1041 conf_pci_img_ctrl1_out[0],
1042 conf_pci_img_ctrl0_out[0]
1045 wire [5:0] pciu_at_en_in = {
1046 conf_pci_img_ctrl5_out[1],
1047 conf_pci_img_ctrl4_out[1],
1048 conf_pci_img_ctrl3_out[1],
1049 conf_pci_img_ctrl2_out[1],
1050 conf_pci_img_ctrl1_out[1],
1051 conf_pci_img_ctrl0_out[1]
1054 wire pciu_mem_enable_in = conf_mem_space_enable_out ;
1055 wire pciu_io_enable_in = conf_io_space_enable_out ;
1057 wire pciu_wbw_fifo_empty_in = wbu_wbw_fifo_empty_out ;
1058 wire pciu_wbu_del_read_comp_pending_in = wbu_del_read_comp_pending_out ;
1059 wire pciu_wbu_frame_en_in = out_bckp_frame_en_out ;
1062 wire [31:0] pciu_conf_data_in = conf_r_data_out ;
1065 wire [31:0] pciu_conf_data_in = conf_w_data_out ;
1069 wire [pci_ba0_width - 1:0] pciu_bar0_in = conf_pci_ba0_out ;
1070 wire [pci_ba1_5_width - 1:0] pciu_bar1_in = conf_pci_ba1_out ;
1071 wire [pci_ba1_5_width - 1:0] pciu_bar2_in = conf_pci_ba2_out ;
1072 wire [pci_ba1_5_width - 1:0] pciu_bar3_in = conf_pci_ba3_out ;
1073 wire [pci_ba1_5_width - 1:0] pciu_bar4_in = conf_pci_ba4_out ;
1074 wire [pci_ba1_5_width - 1:0] pciu_bar5_in = conf_pci_ba5_out ;
1075 wire [pci_ba1_5_width - 1:0] pciu_am0_in = conf_pci_am0_out ;
1076 wire [pci_ba1_5_width - 1:0] pciu_am1_in = conf_pci_am1_out ;
1077 wire [pci_ba1_5_width - 1:0] pciu_am2_in = conf_pci_am2_out ;
1078 wire [pci_ba1_5_width - 1:0] pciu_am3_in = conf_pci_am3_out ;
1079 wire [pci_ba1_5_width - 1:0] pciu_am4_in = conf_pci_am4_out ;
1080 wire [pci_ba1_5_width - 1:0] pciu_am5_in = conf_pci_am5_out ;
1081 wire [pci_ba1_5_width - 1:0] pciu_ta0_in = conf_pci_ta0_out ;
1082 wire [pci_ba1_5_width - 1:0] pciu_ta1_in = conf_pci_ta1_out ;
1083 wire [pci_ba1_5_width - 1:0] pciu_ta2_in = conf_pci_ta2_out ;
1084 wire [pci_ba1_5_width - 1:0] pciu_ta3_in = conf_pci_ta3_out ;
1085 wire [pci_ba1_5_width - 1:0] pciu_ta4_in = conf_pci_ta4_out ;
1086 wire [pci_ba1_5_width - 1:0] pciu_ta5_in = conf_pci_ta5_out ;
1088 wire [7:0] pciu_cache_line_size_in = conf_cache_line_size_to_wb_out ;
1089 wire pciu_cache_lsize_not_zero_in = conf_cache_lsize_not_zero_to_wb_out ;
1091 wire pciu_pciif_frame_in = int_pci_frame ;
1092 wire pciu_pciif_irdy_in = int_pci_irdy ;
1093 wire pciu_pciif_idsel_in = pci_idsel_i ;
1094 wire pciu_pciif_frame_reg_in = in_reg_frame_out ;
1095 wire pciu_pciif_irdy_reg_in = in_reg_irdy_out ;
1096 wire pciu_pciif_idsel_reg_in = in_reg_idsel_out ;
1097 wire [31:0] pciu_pciif_ad_reg_in = in_reg_ad_out ;
1098 wire [3:0] pciu_pciif_cbe_reg_in = in_reg_cbe_out ;
1099 wire [3:0] pciu_pciif_cbe_in = int_pci_cbe ;
1101 wire pciu_pciif_bckp_trdy_en_in = out_bckp_trdy_en_out ;
1102 wire pciu_pciif_bckp_devsel_in = out_bckp_devsel_out ;
1103 wire pciu_pciif_bckp_trdy_in = out_bckp_trdy_out ;
1104 wire pciu_pciif_bckp_stop_in = out_bckp_stop_out ;
1105 wire pciu_pciif_trdy_reg_in = in_reg_trdy_out ;
1106 wire pciu_pciif_stop_reg_in = in_reg_stop_out ;
1108 pci_target_unit pci_target_unit
1111 .wb_clock_in (wb_clk),
1112 .pci_clock_in (pci_clk),
1113 .pciu_wbm_adr_o (pciu_adr_out),
1114 .pciu_wbm_dat_o (pciu_mdata_out),
1115 .pciu_wbm_dat_i (pciu_mdata_in),
1116 .pciu_wbm_cyc_o (pciu_cyc_out),
1117 .pciu_wbm_stb_o (pciu_stb_out),
1118 .pciu_wbm_we_o (pciu_we_out),
1119 .pciu_wbm_cti_o (pciu_cti_out),
1120 .pciu_wbm_bte_o (pciu_bte_out),
1121 .pciu_wbm_sel_o (pciu_sel_out),
1122 .pciu_wbm_ack_i (pciu_ack_in),
1123 .pciu_wbm_rty_i (pciu_rty_in),
1124 .pciu_wbm_err_i (pciu_err_in),
1125 .pciu_mem_enable_in (pciu_mem_enable_in),
1126 .pciu_io_enable_in (pciu_io_enable_in),
1127 .pciu_map_in (pciu_map_in),
1128 .pciu_pref_en_in (pciu_pref_en_in),
1129 .pciu_conf_data_in (pciu_conf_data_in),
1130 .pciu_wbw_fifo_empty_in (pciu_wbw_fifo_empty_in),
1131 .pciu_wbu_del_read_comp_pending_in (pciu_wbu_del_read_comp_pending_in),
1132 .pciu_wbu_frame_en_in (pciu_wbu_frame_en_in),
1133 .pciu_bar0_in (pciu_bar0_in),
1134 .pciu_bar1_in (pciu_bar1_in),
1135 .pciu_bar2_in (pciu_bar2_in),
1136 .pciu_bar3_in (pciu_bar3_in),
1137 .pciu_bar4_in (pciu_bar4_in),
1138 .pciu_bar5_in (pciu_bar5_in),
1139 .pciu_am0_in (pciu_am0_in),
1140 .pciu_am1_in (pciu_am1_in),
1141 .pciu_am2_in (pciu_am2_in),
1142 .pciu_am3_in (pciu_am3_in),
1143 .pciu_am4_in (pciu_am4_in),
1144 .pciu_am5_in (pciu_am5_in),
1145 .pciu_ta0_in (pciu_ta0_in),
1146 .pciu_ta1_in (pciu_ta1_in),
1147 .pciu_ta2_in (pciu_ta2_in),
1148 .pciu_ta3_in (pciu_ta3_in),
1149 .pciu_ta4_in (pciu_ta4_in),
1150 .pciu_ta5_in (pciu_ta5_in),
1151 .pciu_at_en_in (pciu_at_en_in),
1152 .pciu_cache_line_size_in (pciu_cache_line_size_in),
1153 .pciu_cache_lsize_not_zero_in (pciu_cache_lsize_not_zero_in),
1154 .pciu_pciif_frame_in (pciu_pciif_frame_in),
1155 .pciu_pciif_irdy_in (pciu_pciif_irdy_in),
1156 .pciu_pciif_idsel_in (pciu_pciif_idsel_in),
1157 .pciu_pciif_frame_reg_in (pciu_pciif_frame_reg_in),
1158 .pciu_pciif_irdy_reg_in (pciu_pciif_irdy_reg_in),
1159 .pciu_pciif_idsel_reg_in (pciu_pciif_idsel_reg_in),
1160 .pciu_pciif_ad_reg_in (pciu_pciif_ad_reg_in),
1161 .pciu_pciif_cbe_reg_in (pciu_pciif_cbe_reg_in),
1162 .pciu_pciif_cbe_in (pciu_pciif_cbe_in),
1163 .pciu_pciif_bckp_trdy_en_in (pciu_pciif_bckp_trdy_en_in),
1164 .pciu_pciif_bckp_devsel_in (pciu_pciif_bckp_devsel_in),
1165 .pciu_pciif_bckp_trdy_in (pciu_pciif_bckp_trdy_in),
1166 .pciu_pciif_bckp_stop_in (pciu_pciif_bckp_stop_in),
1167 .pciu_pciif_trdy_reg_in (pciu_pciif_trdy_reg_in),
1168 .pciu_pciif_stop_reg_in (pciu_pciif_stop_reg_in),
1169 .pciu_pciif_trdy_out (pciu_pciif_trdy_out),
1170 .pciu_pciif_stop_out (pciu_pciif_stop_out),
1171 .pciu_pciif_devsel_out (pciu_pciif_devsel_out),
1172 .pciu_pciif_trdy_en_out (pciu_pciif_trdy_en_out),
1173 .pciu_pciif_stop_en_out (pciu_pciif_stop_en_out),
1174 .pciu_pciif_devsel_en_out (pciu_pciif_devsel_en_out),
1175 .pciu_ad_load_out (pciu_ad_load_out),
1176 .pciu_ad_load_on_transfer_out (pciu_ad_load_on_transfer_out),
1177 .pciu_pciif_ad_out (pciu_pciif_ad_out),
1178 .pciu_pciif_ad_en_out (pciu_pciif_ad_en_out),
1179 .pciu_pciif_tabort_set_out (pciu_pciif_tabort_set_out),
1180 .pciu_err_addr_out (pciu_err_addr_out),
1181 .pciu_err_bc_out (pciu_err_bc_out),
1182 .pciu_err_data_out (pciu_err_data_out),
1183 .pciu_err_be_out (pciu_err_be_out),
1184 .pciu_err_signal_out (pciu_err_signal_out),
1185 .pciu_err_source_out (pciu_err_source_out),
1186 .pciu_err_rty_exp_out (pciu_err_rty_exp_out),
1187 .pciu_conf_offset_out (pciu_conf_offset_out),
1188 .pciu_conf_renable_out (pciu_conf_renable_out),
1189 .pciu_conf_wenable_out (pciu_conf_wenable_out),
1190 .pciu_conf_be_out (pciu_conf_be_out),
1191 .pciu_conf_data_out (pciu_conf_data_out),
1192 .pciu_pci_drcomp_pending_out (pciu_pci_drcomp_pending_out),
1193 .pciu_pciw_fifo_empty_out (pciu_pciw_fifo_empty_out)
1197 .mbist_si_i (mbist_so_o_internal),
1198 .mbist_so_o (mbist_so_o),
1199 .mbist_ctrl_i (mbist_ctrl_i)
1204 // CONFIGURATION SPACE INPUTS
1207 wire [11:0] conf_w_addr_in = wbu_conf_offset_out ;
1208 wire [31:0] conf_w_data_in = wbu_conf_data_out ;
1209 wire conf_w_we_in = wbu_conf_wenable_out ;
1210 wire conf_w_re_in = wbu_conf_renable_out ;
1211 wire [3:0] conf_w_be_in = wbu_conf_be_out ;
1212 wire conf_w_clock = wb_clk ;
1213 wire [11:0] conf_r_addr_in = pciu_conf_offset_out ;
1214 wire conf_r_re_in = pciu_conf_renable_out ;
1219 wire [11:0] conf_r_addr_in = wbu_conf_offset_out ;
1220 wire conf_r_re_in = wbu_conf_renable_out ;
1221 wire conf_w_clock = pci_clk ;
1222 wire [11:0] conf_w_addr_in = pciu_conf_offset_out ;
1223 wire [31:0] conf_w_data_in = pciu_conf_data_out ;
1224 wire conf_w_we_in = pciu_conf_wenable_out ;
1225 wire conf_w_re_in = pciu_conf_renable_out ;
1226 wire [3:0] conf_w_be_in = pciu_conf_be_out ;
1232 wire conf_perr_in = parchk_par_err_detect_out ;
1233 wire conf_serr_in = parchk_sig_serr_out ;
1234 wire conf_master_abort_recv_in = wbu_mabort_rec_out ;
1235 wire conf_target_abort_recv_in = wbu_tabort_rec_out ;
1236 wire conf_target_abort_set_in = pciu_pciif_tabort_set_out ;
1238 wire conf_master_data_par_err_in = parchk_perr_mas_detect_out ;
1240 wire [3:0] conf_pci_err_be_in = pciu_err_be_out ;
1241 wire [3:0] conf_pci_err_bc_in = pciu_err_bc_out;
1242 wire conf_pci_err_es_in = pciu_err_source_out ;
1243 wire conf_pci_err_rty_exp_in = pciu_err_rty_exp_out ;
1244 wire conf_pci_err_sig_in = pciu_err_signal_out ;
1245 wire [31:0] conf_pci_err_addr_in = pciu_err_addr_out ;
1246 wire [31:0] conf_pci_err_data_in = pciu_err_data_out ;
1248 wire [3:0] conf_wb_err_be_in = out_bckp_cbe_out ;
1249 wire [3:0] conf_wb_err_bc_in = wbu_err_bc_out ;
1250 wire conf_wb_err_rty_exp_in = wbu_err_rty_exp_out ;
1251 wire conf_wb_err_es_in = wbu_err_source_out ;
1252 wire conf_wb_err_sig_in = wbu_err_signal_out ;
1253 wire [31:0] conf_wb_err_addr_in = wbu_err_addr_out ;
1254 wire [31:0] conf_wb_err_data_in = out_bckp_ad_out ;
1256 wire conf_isr_int_prop_in = pci_into_conf_isr_int_prop_out ;
1257 wire conf_par_err_int_in = parchk_perr_mas_detect_out ;
1258 wire conf_sys_err_int_in = parchk_sig_serr_out ;
1260 pci_conf_space configuration(
1264 .w_conf_address_in (conf_w_addr_in),
1265 .w_conf_data_in (conf_w_data_in),
1266 .w_conf_data_out (conf_w_data_out),
1267 .r_conf_address_in (conf_r_addr_in),
1268 .r_conf_data_out (conf_r_data_out),
1269 .w_we_i (conf_w_we_in),
1270 .w_re (conf_w_re_in),
1271 .r_re (conf_r_re_in),
1272 .w_byte_en_in (conf_w_be_in),
1273 .w_clock (conf_w_clock),
1274 .serr_enable (conf_serr_enable_out),
1275 .perr_response (conf_perr_response_out),
1276 .pci_master_enable (conf_pci_master_enable_out),
1277 .memory_space_enable (conf_mem_space_enable_out),
1278 .io_space_enable (conf_io_space_enable_out),
1279 .perr_in (conf_perr_in),
1280 .serr_in (conf_serr_in),
1281 .master_abort_recv (conf_master_abort_recv_in),
1282 .target_abort_recv (conf_target_abort_recv_in),
1283 .target_abort_set (conf_target_abort_set_in),
1284 .master_data_par_err (conf_master_data_par_err_in),
1285 .cache_line_size_to_pci (conf_cache_line_size_to_pci_out),
1286 .cache_line_size_to_wb (conf_cache_line_size_to_wb_out),
1287 .cache_lsize_not_zero_to_wb (conf_cache_lsize_not_zero_to_wb_out),
1288 .latency_tim (conf_latency_tim_out),
1289 .pci_base_addr0 (conf_pci_ba0_out),
1290 .pci_base_addr1 (conf_pci_ba1_out),
1291 .pci_base_addr2 (conf_pci_ba2_out),
1292 .pci_base_addr3 (conf_pci_ba3_out),
1293 .pci_base_addr4 (conf_pci_ba4_out),
1294 .pci_base_addr5 (conf_pci_ba5_out),
1295 .pci_memory_io0 (conf_pci_mem_io0_out),
1296 .pci_memory_io1 (conf_pci_mem_io1_out),
1297 .pci_memory_io2 (conf_pci_mem_io2_out),
1298 .pci_memory_io3 (conf_pci_mem_io3_out),
1299 .pci_memory_io4 (conf_pci_mem_io4_out),
1300 .pci_memory_io5 (conf_pci_mem_io5_out),
1301 .pci_addr_mask0 (conf_pci_am0_out),
1302 .pci_addr_mask1 (conf_pci_am1_out),
1303 .pci_addr_mask2 (conf_pci_am2_out),
1304 .pci_addr_mask3 (conf_pci_am3_out),
1305 .pci_addr_mask4 (conf_pci_am4_out),
1306 .pci_addr_mask5 (conf_pci_am5_out),
1307 .pci_tran_addr0 (conf_pci_ta0_out),
1308 .pci_tran_addr1 (conf_pci_ta1_out),
1309 .pci_tran_addr2 (conf_pci_ta2_out),
1310 .pci_tran_addr3 (conf_pci_ta3_out),
1311 .pci_tran_addr4 (conf_pci_ta4_out),
1312 .pci_tran_addr5 (conf_pci_ta5_out),
1313 .pci_img_ctrl0 (conf_pci_img_ctrl0_out),
1314 .pci_img_ctrl1 (conf_pci_img_ctrl1_out),
1315 .pci_img_ctrl2 (conf_pci_img_ctrl2_out),
1316 .pci_img_ctrl3 (conf_pci_img_ctrl3_out),
1317 .pci_img_ctrl4 (conf_pci_img_ctrl4_out),
1318 .pci_img_ctrl5 (conf_pci_img_ctrl5_out),
1319 .pci_error_be (conf_pci_err_be_in),
1320 .pci_error_bc (conf_pci_err_bc_in),
1321 .pci_error_rty_exp (conf_pci_err_rty_exp_in),
1322 .pci_error_es (conf_pci_err_es_in),
1323 .pci_error_sig (conf_pci_err_sig_in),
1324 .pci_error_addr (conf_pci_err_addr_in),
1325 .pci_error_data (conf_pci_err_data_in),
1326 .wb_base_addr0 (conf_wb_ba0_out),
1327 .wb_base_addr1 (conf_wb_ba1_out),
1328 .wb_base_addr2 (conf_wb_ba2_out),
1329 .wb_base_addr3 (conf_wb_ba3_out),
1330 .wb_base_addr4 (conf_wb_ba4_out),
1331 .wb_base_addr5 (conf_wb_ba5_out),
1332 .wb_memory_io0 (conf_wb_mem_io0_out),
1333 .wb_memory_io1 (conf_wb_mem_io1_out),
1334 .wb_memory_io2 (conf_wb_mem_io2_out),
1335 .wb_memory_io3 (conf_wb_mem_io3_out),
1336 .wb_memory_io4 (conf_wb_mem_io4_out),
1337 .wb_memory_io5 (conf_wb_mem_io5_out),
1338 .wb_addr_mask0 (conf_wb_am0_out),
1339 .wb_addr_mask1 (conf_wb_am1_out),
1340 .wb_addr_mask2 (conf_wb_am2_out),
1341 .wb_addr_mask3 (conf_wb_am3_out),
1342 .wb_addr_mask4 (conf_wb_am4_out),
1343 .wb_addr_mask5 (conf_wb_am5_out),
1344 .wb_tran_addr0 (conf_wb_ta0_out),
1345 .wb_tran_addr1 (conf_wb_ta1_out),
1346 .wb_tran_addr2 (conf_wb_ta2_out),
1347 .wb_tran_addr3 (conf_wb_ta3_out),
1348 .wb_tran_addr4 (conf_wb_ta4_out),
1349 .wb_tran_addr5 (conf_wb_ta5_out),
1350 .wb_img_ctrl0 (conf_wb_img_ctrl0_out),
1351 .wb_img_ctrl1 (conf_wb_img_ctrl1_out),
1352 .wb_img_ctrl2 (conf_wb_img_ctrl2_out),
1353 .wb_img_ctrl3 (conf_wb_img_ctrl3_out),
1354 .wb_img_ctrl4 (conf_wb_img_ctrl4_out),
1355 .wb_img_ctrl5 (conf_wb_img_ctrl5_out),
1356 .wb_error_be (conf_wb_err_be_in),
1357 .wb_error_bc (conf_wb_err_bc_in),
1358 .wb_error_rty_exp (conf_wb_err_rty_exp_in),
1359 .wb_error_es (conf_wb_err_es_in),
1360 .wb_error_sig (conf_wb_err_sig_in),
1361 .wb_error_addr (conf_wb_err_addr_in),
1362 .wb_error_data (conf_wb_err_data_in),
1363 .config_addr (conf_ccyc_addr_out),
1364 .icr_soft_res (conf_soft_res_out),
1365 .int_out (conf_int_out),
1366 .isr_int_prop (conf_isr_int_prop_in),
1367 .isr_par_err_int (conf_par_err_int_in),
1368 .isr_sys_err_int (conf_sys_err_int_in),
1370 .pci_init_complete_out (conf_pci_init_complete_out),
1371 .wb_init_complete_out (conf_wb_init_complete_out)
1373 `ifdef PCI_CPCI_HS_IMPLEMENT
1375 .pci_cpci_hs_enum_oe_o (pci_cpci_hs_enum_oe_o) ,
1376 .pci_cpci_hs_led_oe_o (pci_cpci_hs_led_oe_o ) ,
1377 .pci_cpci_hs_es_i (pci_cpci_hs_es_i)
1382 // Serial power on configuration interface
1383 .spoci_scl_oe_o (spoci_scl_oe_o ) ,
1384 .spoci_sda_i (spoci_sda_i ) ,
1385 .spoci_sda_oe_o (spoci_sda_oe_o )
1389 // pci data io multiplexer inputs
1390 wire pci_mux_tar_ad_en_in = pciu_pciif_ad_en_out ;
1391 wire pci_mux_tar_ad_en_reg_in = out_bckp_tar_ad_en_out ;
1392 wire [31:0] pci_mux_tar_ad_in = pciu_pciif_ad_out ;
1393 wire pci_mux_devsel_in = pciu_pciif_devsel_out ;
1394 wire pci_mux_devsel_en_in = pciu_pciif_devsel_en_out ;
1395 wire pci_mux_trdy_in = pciu_pciif_trdy_out ;
1396 wire pci_mux_trdy_en_in = pciu_pciif_trdy_en_out ;
1397 wire pci_mux_stop_in = pciu_pciif_stop_out ;
1398 wire pci_mux_stop_en_in = pciu_pciif_stop_en_out ;
1399 wire pci_mux_tar_load_in = pciu_ad_load_out ;
1400 wire pci_mux_tar_load_on_transfer_in = pciu_ad_load_on_transfer_out ;
1402 wire pci_mux_mas_ad_en_in = wbu_pciif_ad_en_out ;
1403 wire [31:0] pci_mux_mas_ad_in = wbu_pciif_ad_out ;
1405 wire pci_mux_frame_in = wbu_pciif_frame_out ;
1406 wire pci_mux_frame_en_in = wbu_pciif_frame_en_out ;
1407 wire pci_mux_irdy_in = wbu_pciif_irdy_out;
1408 wire pci_mux_irdy_en_in = wbu_pciif_irdy_en_out;
1409 wire pci_mux_mas_load_in = wbu_ad_load_out ;
1410 wire pci_mux_mas_load_on_transfer_in = wbu_ad_load_on_transfer_out ;
1411 wire [3:0] pci_mux_cbe_in = wbu_pciif_cbe_out ;
1412 wire pci_mux_cbe_en_in = wbu_pciif_cbe_en_out ;
1414 wire pci_mux_par_in = parchk_pci_par_out ;
1415 wire pci_mux_par_en_in = parchk_pci_par_en_out ;
1416 wire pci_mux_perr_in = parchk_pci_perr_out ;
1417 wire pci_mux_perr_en_in = parchk_pci_perr_en_out ;
1418 wire pci_mux_serr_in = parchk_pci_serr_out ;
1419 wire pci_mux_serr_en_in = parchk_pci_serr_en_out;
1421 wire pci_mux_req_in = wbu_pciif_req_out ;
1422 wire pci_mux_frame_load_in = wbu_pciif_frame_load_out ;
1424 wire pci_mux_pci_irdy_in = int_pci_irdy ;
1425 wire pci_mux_pci_trdy_in = int_pci_trdy ;
1426 wire pci_mux_pci_frame_in = int_pci_frame ;
1427 wire pci_mux_pci_stop_in = int_pci_stop ;
1429 wire pci_mux_init_complete_in = conf_pci_init_complete_out ;
1431 pci_io_mux pci_io_mux
1435 .frame_in (pci_mux_frame_in),
1436 .frame_en_in (pci_mux_frame_en_in),
1437 .frame_load_in (pci_mux_frame_load_in),
1438 .irdy_in (pci_mux_irdy_in),
1439 .irdy_en_in (pci_mux_irdy_en_in),
1440 .devsel_in (pci_mux_devsel_in),
1441 .devsel_en_in (pci_mux_devsel_en_in),
1442 .trdy_in (pci_mux_trdy_in),
1443 .trdy_en_in (pci_mux_trdy_en_in),
1444 .stop_in (pci_mux_stop_in),
1445 .stop_en_in (pci_mux_stop_en_in),
1446 .master_load_in (pci_mux_mas_load_in),
1447 .master_load_on_transfer_in (pci_mux_mas_load_on_transfer_in),
1448 .target_load_in (pci_mux_tar_load_in),
1449 .target_load_on_transfer_in (pci_mux_tar_load_on_transfer_in),
1450 .cbe_in (pci_mux_cbe_in),
1451 .cbe_en_in (pci_mux_cbe_en_in),
1452 .mas_ad_in (pci_mux_mas_ad_in),
1453 .tar_ad_in (pci_mux_tar_ad_in),
1455 .mas_ad_en_in (pci_mux_mas_ad_en_in),
1456 .tar_ad_en_in (pci_mux_tar_ad_en_in),
1457 .tar_ad_en_reg_in (pci_mux_tar_ad_en_reg_in),
1459 .par_in (pci_mux_par_in),
1460 .par_en_in (pci_mux_par_en_in),
1461 .perr_in (pci_mux_perr_in),
1462 .perr_en_in (pci_mux_perr_en_in),
1463 .serr_in (pci_mux_serr_in),
1464 .serr_en_in (pci_mux_serr_en_in),
1466 .frame_en_out (pci_mux_frame_en_out),
1467 .irdy_en_out (pci_mux_irdy_en_out),
1468 .devsel_en_out (pci_mux_devsel_en_out),
1469 .trdy_en_out (pci_mux_trdy_en_out),
1470 .stop_en_out (pci_mux_stop_en_out),
1471 .cbe_en_out (pci_mux_cbe_en_out),
1472 .ad_en_out (pci_mux_ad_en_out),
1474 .frame_out (pci_mux_frame_out),
1475 .irdy_out (pci_mux_irdy_out),
1476 .devsel_out (pci_mux_devsel_out),
1477 .trdy_out (pci_mux_trdy_out),
1478 .stop_out (pci_mux_stop_out),
1479 .cbe_out (pci_mux_cbe_out),
1480 .ad_out (pci_mux_ad_out),
1481 .ad_load_out (pci_mux_ad_load_out),
1483 .par_out (pci_mux_par_out),
1484 .par_en_out (pci_mux_par_en_out),
1485 .perr_out (pci_mux_perr_out),
1486 .perr_en_out (pci_mux_perr_en_out),
1487 .serr_out (pci_mux_serr_out),
1488 .serr_en_out (pci_mux_serr_en_out),
1489 .req_in (pci_mux_req_in),
1490 .req_out (pci_mux_req_out),
1491 .req_en_out (pci_mux_req_en_out),
1492 .pci_irdy_in (pci_mux_pci_irdy_in),
1493 .pci_trdy_in (pci_mux_pci_trdy_in),
1494 .pci_frame_in (pci_mux_pci_frame_in),
1495 .pci_stop_in (pci_mux_pci_stop_in),
1496 .ad_en_unregistered_out (pci_mux_ad_en_unregistered_out),
1498 .init_complete_in (pci_mux_init_complete_in)
1501 pci_cur_out_reg output_backup
1505 .frame_in (pci_mux_frame_in),
1506 .frame_en_in (pci_mux_frame_en_in),
1507 .frame_load_in (pci_mux_frame_load_in),
1508 .irdy_in (pci_mux_irdy_in),
1509 .irdy_en_in (pci_mux_irdy_en_in),
1510 .devsel_in (pci_mux_devsel_in),
1511 .trdy_in (pci_mux_trdy_in),
1512 .trdy_en_in (pci_mux_trdy_en_in),
1513 .stop_in (pci_mux_stop_in),
1514 .ad_load_in (pci_mux_ad_load_out),
1515 .cbe_in (pci_mux_cbe_in),
1516 .cbe_en_in (pci_mux_cbe_en_in),
1517 .mas_ad_in (pci_mux_mas_ad_in),
1518 .tar_ad_in (pci_mux_tar_ad_in),
1520 .mas_ad_en_in (pci_mux_mas_ad_en_in),
1521 .tar_ad_en_in (pci_mux_tar_ad_en_in),
1522 .ad_en_unregistered_in (pci_mux_ad_en_unregistered_out),
1524 .par_in (pci_mux_par_in),
1525 .par_en_in (pci_mux_par_en_in),
1526 .perr_in (pci_mux_perr_in),
1527 .perr_en_in (pci_mux_perr_en_in),
1528 .serr_in (pci_mux_serr_in),
1529 .serr_en_in (pci_mux_serr_en_in),
1531 .frame_out (out_bckp_frame_out),
1532 .frame_en_out (out_bckp_frame_en_out),
1533 .irdy_out (out_bckp_irdy_out),
1534 .irdy_en_out (out_bckp_irdy_en_out),
1535 .devsel_out (out_bckp_devsel_out),
1536 .trdy_out (out_bckp_trdy_out),
1537 .trdy_en_out (out_bckp_trdy_en_out),
1538 .stop_out (out_bckp_stop_out),
1539 .cbe_out (out_bckp_cbe_out),
1540 .ad_out (out_bckp_ad_out),
1541 .ad_en_out (out_bckp_ad_en_out),
1542 .cbe_en_out (out_bckp_cbe_en_out),
1543 .tar_ad_en_out (out_bckp_tar_ad_en_out),
1544 .mas_ad_en_out (out_bckp_mas_ad_en_out),
1546 .par_out (out_bckp_par_out),
1547 .par_en_out (out_bckp_par_en_out),
1548 .perr_out (out_bckp_perr_out),
1549 .perr_en_out (out_bckp_perr_en_out),
1550 .serr_out (out_bckp_serr_out),
1551 .serr_en_out (out_bckp_serr_en_out)
1554 // PARITY CHECKER INPUTS
1555 wire parchk_pci_par_in = int_pci_par ;
1556 wire parchk_pci_perr_in = int_pci_perr ;
1557 wire parchk_pci_frame_reg_in = in_reg_frame_out ;
1558 wire parchk_pci_frame_en_in = out_bckp_frame_en_out ;
1559 wire parchk_pci_irdy_en_in = out_bckp_irdy_en_out ;
1560 wire parchk_pci_irdy_reg_in = in_reg_irdy_out ;
1561 wire parchk_pci_trdy_reg_in = in_reg_trdy_out ;
1564 wire parchk_pci_trdy_en_in = out_bckp_trdy_en_out ;
1567 wire [31:0] parchk_pci_ad_out_in = out_bckp_ad_out ;
1568 wire [31:0] parchk_pci_ad_reg_in = in_reg_ad_out ;
1569 wire [3:0] parchk_pci_cbe_in_in = int_pci_cbe ;
1570 wire [3:0] parchk_pci_cbe_reg_in = in_reg_cbe_out ;
1571 wire [3:0] parchk_pci_cbe_out_in = out_bckp_cbe_out ;
1572 wire parchk_pci_ad_en_in = out_bckp_ad_en_out ;
1573 wire parchk_par_err_response_in = conf_perr_response_out ;
1574 wire parchk_serr_enable_in = conf_serr_enable_out ;
1576 wire parchk_pci_perr_out_in = out_bckp_perr_out ;
1577 wire parchk_pci_serr_en_in = out_bckp_serr_en_out ;
1578 wire parchk_pci_serr_out_in = out_bckp_serr_out ;
1579 wire parchk_pci_cbe_en_in = out_bckp_cbe_en_out ;
1581 wire parchk_pci_par_en_in = out_bckp_par_en_out ;
1583 pci_parity_check parity_checker
1587 .pci_par_in (parchk_pci_par_in),
1588 .pci_par_out (parchk_pci_par_out),
1589 .pci_par_en_out (parchk_pci_par_en_out),
1590 .pci_par_en_in (parchk_pci_par_en_in),
1591 .pci_perr_in (parchk_pci_perr_in),
1592 .pci_perr_out (parchk_pci_perr_out),
1593 .pci_perr_en_out (parchk_pci_perr_en_out),
1594 .pci_perr_out_in (parchk_pci_perr_out_in),
1595 .pci_serr_out (parchk_pci_serr_out),
1596 .pci_serr_out_in (parchk_pci_serr_out_in),
1597 .pci_serr_en_out (parchk_pci_serr_en_out),
1598 .pci_serr_en_in (parchk_pci_serr_en_in),
1599 .pci_frame_reg_in (parchk_pci_frame_reg_in),
1600 .pci_frame_en_in (parchk_pci_frame_en_in),
1601 .pci_irdy_en_in (parchk_pci_irdy_en_in),
1602 .pci_irdy_reg_in (parchk_pci_irdy_reg_in),
1603 .pci_trdy_reg_in (parchk_pci_trdy_reg_in),
1604 .pci_trdy_en_in (parchk_pci_trdy_en_in),
1605 .pci_ad_out_in (parchk_pci_ad_out_in),
1606 .pci_ad_reg_in (parchk_pci_ad_reg_in),
1607 .pci_cbe_in_in (parchk_pci_cbe_in_in),
1608 .pci_cbe_reg_in (parchk_pci_cbe_reg_in),
1609 .pci_cbe_en_in (parchk_pci_cbe_en_in),
1610 .pci_cbe_out_in (parchk_pci_cbe_out_in),
1611 .pci_ad_en_in (parchk_pci_ad_en_in),
1612 .par_err_response_in (parchk_par_err_response_in),
1613 .par_err_detect_out (parchk_par_err_detect_out),
1614 .perr_mas_detect_out (parchk_perr_mas_detect_out),
1615 .serr_enable_in (parchk_serr_enable_in),
1616 .sig_serr_out (parchk_sig_serr_out)
1619 wire in_reg_gnt_in = pci_gnt_i ;
1620 wire in_reg_frame_in = int_pci_frame ;
1621 wire in_reg_irdy_in = int_pci_irdy ;
1622 wire in_reg_trdy_in = int_pci_trdy ;
1623 wire in_reg_stop_in = int_pci_stop ;
1624 wire in_reg_devsel_in = int_pci_devsel ;
1625 wire in_reg_idsel_in = pci_idsel_i ;
1626 wire [31:0] in_reg_ad_in = pci_ad_i ;
1627 wire [3:0] in_reg_cbe_in = int_pci_cbe ;
1629 pci_in_reg input_register
1633 .init_complete_in (conf_pci_init_complete_out),
1635 .pci_gnt_in (in_reg_gnt_in),
1636 .pci_frame_in (in_reg_frame_in),
1637 .pci_irdy_in (in_reg_irdy_in),
1638 .pci_trdy_in (in_reg_trdy_in),
1639 .pci_stop_in (in_reg_stop_in),
1640 .pci_devsel_in (in_reg_devsel_in),
1641 .pci_idsel_in (in_reg_idsel_in),
1642 .pci_ad_in (in_reg_ad_in),
1643 .pci_cbe_in (in_reg_cbe_in),
1645 .pci_gnt_reg_out (in_reg_gnt_out),
1646 .pci_frame_reg_out (in_reg_frame_out),
1647 .pci_irdy_reg_out (in_reg_irdy_out),
1648 .pci_trdy_reg_out (in_reg_trdy_out),
1649 .pci_stop_reg_out (in_reg_stop_out),
1650 .pci_devsel_reg_out (in_reg_devsel_out),
1651 .pci_idsel_reg_out (in_reg_idsel_out),
1652 .pci_ad_reg_out (in_reg_ad_out),
1653 .pci_cbe_reg_out (in_reg_cbe_out)
projects / raggedstone / blob