1 //////////////////////////////////////////////////////////////////////
3 //// File name "mas_ad_load_crit.v" ////
5 //// This file is part of the "PCI bridge" project ////
6 //// http://www.opencores.org/cores/pci/ ////
9 //// - Miha Dolenc (mihad@opencores.org) ////
11 //// All additional information is avaliable in the README ////
15 //////////////////////////////////////////////////////////////////////
17 //// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
19 //// This source file may be used and distributed without ////
20 //// restriction provided that this copyright statement is not ////
21 //// removed from the file and that any derivative work contains ////
22 //// the original copyright notice and the associated disclaimer. ////
24 //// This source file is free software; you can redistribute it ////
25 //// and/or modify it under the terms of the GNU Lesser General ////
26 //// Public License as published by the Free Software Foundation; ////
27 //// either version 2.1 of the License, or (at your option) any ////
28 //// later version. ////
30 //// This source is distributed in the hope that it will be ////
31 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
32 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
33 //// PURPOSE. See the GNU Lesser General Public License for more ////
36 //// You should have received a copy of the GNU Lesser General ////
37 //// Public License along with this source; if not, download it ////
38 //// from http://www.opencores.org/lgpl.shtml ////
40 //////////////////////////////////////////////////////////////////////
42 // CVS Revision History
44 // $Log: pci_mas_ad_load_crit.v,v $
45 // Revision 1.1 2007-03-20 17:50:56 sithglan
48 // Revision 1.1 2003/01/27 16:49:31 mihad
49 // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
51 // Revision 1.1 2002/02/01 14:43:31 mihad
52 // *** empty log message ***
55 // synopsys translate_off
56 `include "timescale.v"
57 // synopsys translate_on
59 // module is included for loading output flip - flops by monitoring timing critical GNT pci input
60 module pci_mas_ad_load_crit
72 assign ad_load_out = ad_load_in || ( ad_load_on_grant_in && !pci_gnt_in ) ;