use internal clock
[raggedstone] / heartbeat / source / top_raggedstone.vhd
1 --+-------------------------------------------------------------------------------------------------+
2 --| |
3 --| File: top.vhd |
4 --| |
5 --| Components: pci32lite.vhd |
6 --| pciwbsequ.vhd |
7 --| pcidmux.vhd |
8 --| pciregs.vhd |
9 --| pcipargen.vhd |
10 --| -- Libs -- |
11 --| ona.vhd |
12 --| |
13 --| Description: RS1 PCI Demo : (TOP) Main file. |
14 --| |
15 --| |
16 --| |
17 --+-------------------------------------------------------------------------------------------------+
18 --| |
19 --| Revision history : |
20 --| Date Version Author Description |
21 --| |
22 --| |
23 --| To do: |
24 --| |
25 --+-------------------------------------------------------------------------------------------------+
26
27
28 --+-----------------------------------------------------------------------------+
29 --| LIBRARIES |
30 --+-----------------------------------------------------------------------------+
31
32 library ieee;
33 use ieee.std_logic_1164.all;
34 use ieee.std_logic_arith.all;
35 use ieee.std_logic_unsigned.all;
36
37 --+-----------------------------------------------------------------------------+
38 --| ENTITY |
39 --+-----------------------------------------------------------------------------+
40
41 entity raggedstone is
42 port (
43
44 -- General
45 PCI_CLK : in std_logic;
46 PCI_nRES : in std_logic;
47 PCI_nREQ : out std_logic;
48
49 -- PCI target 32bits
50 PCI_AD : inout std_logic_vector(31 downto 0);
51 PCI_CBE : in std_logic_vector(3 downto 0);
52 PCI_PAR : out std_logic;
53 PCI_nFRAME : in std_logic;
54 PCI_nIRDY : in std_logic;
55 PCI_nTRDY : out std_logic;
56 PCI_nDEVSEL : out std_logic;
57 PCI_nSTOP : out std_logic;
58 PCI_IDSEL : in std_logic;
59 PCI_nPERR : out std_logic;
60 PCI_nSERR : out std_logic;
61 PCI_nINT : out std_logic;
62
63 -- debug signals
64 LED3 : out std_logic;
65 LED2 : out std_logic;
66 LED4 : out std_logic;
67 LED5 : out std_logic
68 -- IDE1 : out std_logic;
69 -- IDE2 : out std_logic;
70 -- IDE3 : out std_logic;
71 -- IDE4 : out std_logic
72
73 );
74 end raggedstone;
75
76
77 --+-----------------------------------------------------------------------------+
78 --| ARCHITECTURE |
79 --+-----------------------------------------------------------------------------+
80
81 architecture raggedstone_arch of raggedstone is
82
83
84 --+-----------------------------------------------------------------------------+
85 --| COMPONENTS |
86 --+-----------------------------------------------------------------------------+
87
88 component pci32tlite
89 port (
90
91 -- General
92 clk33 : in std_logic;
93 nrst : in std_logic;
94
95 -- PCI target 32bits
96 ad : inout std_logic_vector(31 downto 0);
97 cbe : in std_logic_vector(3 downto 0);
98 par : out std_logic;
99 frame : in std_logic;
100 irdy : in std_logic;
101 trdy : out std_logic;
102 devsel : out std_logic;
103 stop : out std_logic;
104 idsel : in std_logic;
105 perr : out std_logic;
106 serr : out std_logic;
107 intb : out std_logic;
108
109 -- Master whisbone
110 wb_adr_o : out std_logic_vector(24 downto 1);
111 wb_dat_i : in std_logic_vector(15 downto 0);
112 wb_dat_o : out std_logic_vector(15 downto 0);
113 wb_sel_o : out std_logic_vector(1 downto 0);
114 wb_we_o : out std_logic;
115 wb_stb_o : out std_logic;
116 wb_cyc_o : out std_logic;
117 wb_ack_i : in std_logic;
118 wb_err_i : in std_logic;
119 wb_int_i : in std_logic;
120
121 -- debug signals
122 debug_init : out std_logic;
123 debug_access : out std_logic
124
125 );
126 end component;
127
128 component heartbeat
129 port (
130 clk_i : in std_logic;
131 nrst_i : in std_logic;
132 led2_o : out std_logic;
133 led3_o : out std_logic;
134 led4_o : out std_logic;
135 led5_o : out std_logic;
136 led6_o : out std_logic;
137 led7_o : out std_logic;
138 led8_o : out std_logic;
139 led9_o : out std_logic
140 );
141 end component;
142
143
144 --+-----------------------------------------------------------------------------+
145 --| CONSTANTS |
146 --+-----------------------------------------------------------------------------+
147 --+-----------------------------------------------------------------------------+
148 --| SIGNALS |
149 --+-----------------------------------------------------------------------------+
150
151 signal wb_adr : std_logic_vector(24 downto 1);
152 signal wb_dat_out : std_logic_vector(15 downto 0);
153 signal wb_dat_in : std_logic_vector(15 downto 0);
154 signal wb_sel : std_logic_vector(1 downto 0);
155 signal wb_we : std_logic;
156 signal wb_stb : std_logic;
157 signal wb_cyc : std_logic;
158 signal wb_ack : std_logic;
159 signal wb_err : std_logic;
160 signal wb_int : std_logic;
161
162
163 begin
164
165 PCI_nREQ <= '1';
166
167 --+-----------------------------------------+
168 --| PCI Target |
169 --+-----------------------------------------+
170
171 u_pci: component pci32tlite
172 port map(
173 clk33 => PCI_CLK,
174 nrst => PCI_nRES,
175 ad => PCI_AD,
176 cbe => PCI_CBE,
177 par => PCI_PAR,
178 frame => PCI_nFRAME,
179 irdy => PCI_nIRDY,
180 trdy => PCI_nTRDY,
181 devsel => PCI_nDEVSEL,
182 stop => PCI_nSTOP,
183 idsel => PCI_IDSEL,
184 perr => PCI_nPERR,
185 serr => PCI_nSERR,
186 intb => PCI_nINT,
187 wb_adr_o => wb_adr,
188 wb_dat_i => wb_dat_out,
189 wb_dat_o => wb_dat_in,
190 wb_sel_o => wb_sel,
191 wb_we_o => wb_we,
192 wb_stb_o => wb_stb,
193 wb_cyc_o => wb_cyc,
194 wb_ack_i => wb_ack,
195 wb_err_i => wb_err,
196 wb_int_i => wb_int
197 -- debug_init => LED3,
198 -- debug_access => LED2
199 );
200
201 --+-----------------------------------------+
202 --| WB-7seg |
203 --+-----------------------------------------+
204
205 my_heartbeat: component heartbeat
206 port map(
207 clk_i => PCI_CLK,
208 nrst_i => PCI_nRES,
209 led2_o => LED2,
210 led3_o => LED3,
211 led4_o => LED4,
212 led5_o => LED5
213 -- led6_o => IDE1,
214 -- led7_o => IDE2,
215 -- led8_o => IDE3,
216 -- led9_o => IDE4
217 );
218
219 end raggedstone_arch;
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