git.zerfleddert.de Git - raggedstone/blob - dhwk/source/pci/parity.vhd

   1 -- VHDL model created from schematic parity.sch -- Jan 09 09:34:12 2007
   2
   3 LIBRARY ieee;
   4 USE ieee.std_logic_1164.ALL;
   5 USE ieee.numeric_std.ALL;
   6
   7 entity PARITY is
   8         Port ( OE_PCI_PAR : In std_logic;
   9                OE_PCI_PERR : In std_logic;
  10                PA_ER_RE : In std_logic;
  11                PAR_IN : In std_logic_vector (35 downto 0);
  12                PAR_REG : In std_logic;
  13                PCI_CLOCK : In std_logic;
  14                PCI_RSTn : In std_logic;
  15                PERR_CHECK : In std_logic;
  16                SERR_CHECK : In std_logic;
  17                SERR_ENA : In std_logic;
  18                PCI_PAR : InOut std_logic;
  19                PCI_PERRn : Out std_logic;
  20                PCI_SERRn : Out std_logic;
  21                PERR : Out std_logic;
  22                SERR : Out std_logic );
  23 end PARITY;
  24
  25 architecture SCHEMATIC of PARITY is
  26
  27         SIGNAL gnd : std_logic := '0';
  28         SIGNAL vcc : std_logic := '1';
  29
  30         signal PAR_OUT : std_logic_vector (10 downto 0);
  31
  32         component PARITY_OUT
  33                 Port ( OE_PCI_PAR : In std_logic;
  34                        OE_PCI_PERR : In std_logic;
  35                        PA_ER_RE : In std_logic;
  36                        PAR_IN : In std_logic_vector (2 downto 0);
  37                        PAR_REG : In std_logic;
  38                        PCI_CLOCK : In std_logic;
  39                        PCI_PAR_IN : In std_logic;
  40                        PCI_RSTn : In std_logic;
  41                        PERR_CHECK : In std_logic;
  42                        SERR_CHECK : In std_logic;
  43                        SERR_ENA : In std_logic;
  44                        PCI_PAR : Out std_logic;
  45                        PCI_PERRn : Out std_logic;
  46                        PCI_SERRn : Out std_logic;
  47                        PERR : Out std_logic;
  48                        SERR : Out std_logic );
  49         end component;
  50
  51         component PARITY_4
  52                 Port ( PAR_IN : In std_logic_vector (3 downto 0);
  53                        PAR_OUT : Out std_logic );
  54         end component;
  55
  56 begin
  57
  58         I12 : PARITY_OUT
  59         Port Map ( OE_PCI_PAR=>OE_PCI_PAR, OE_PCI_PERR=>OE_PCI_PERR,
  60                    PA_ER_RE=>PA_ER_RE,
  61                    PAR_IN(2 downto 0)=>PAR_OUT(10 downto 8),
  62                    PAR_REG=>PAR_REG, PCI_CLOCK=>PCI_CLOCK,
  63                    PCI_PAR_IN=>PCI_PAR, PCI_RSTn=>PCI_RSTn,
  64                    PERR_CHECK=>PERR_CHECK, SERR_CHECK=>SERR_CHECK,
  65                    SERR_ENA=>SERR_ENA, PCI_PAR=>PCI_PAR,
  66                    PCI_PERRn=>PCI_PERRn, PCI_SERRn=>PCI_SERRn, PERR=>PERR,
  67                    SERR=>SERR );
  68         I9 : PARITY_4
  69         Port Map ( PAR_IN(3 downto 0)=>PAR_IN(35 downto 32),
  70                    PAR_OUT=>PAR_OUT(8) );
  71         I11 : PARITY_4
  72         Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(7 downto 4),
  73                    PAR_OUT=>PAR_OUT(10) );
  74         I8 : PARITY_4
  75         Port Map ( PAR_IN(3 downto 0)=>PAR_IN(31 downto 28),
  76                    PAR_OUT=>PAR_OUT(7) );
  77         I7 : PARITY_4
  78         Port Map ( PAR_IN(3 downto 0)=>PAR_IN(27 downto 24),
  79                    PAR_OUT=>PAR_OUT(6) );
  80         I6 : PARITY_4
  81         Port Map ( PAR_IN(3 downto 0)=>PAR_IN(23 downto 20),
  82                    PAR_OUT=>PAR_OUT(5) );
  83         I5 : PARITY_4
  84         Port Map ( PAR_IN(3 downto 0)=>PAR_IN(19 downto 16),
  85                    PAR_OUT=>PAR_OUT(4) );
  86         I4 : PARITY_4
  87         Port Map ( PAR_IN(3 downto 0)=>PAR_IN(15 downto 12),
  88                    PAR_OUT=>PAR_OUT(3) );
  89         I3 : PARITY_4
  90         Port Map ( PAR_IN(3 downto 0)=>PAR_IN(11 downto 8),
  91                    PAR_OUT=>PAR_OUT(2) );
  92         I2 : PARITY_4
  93         Port Map ( PAR_IN(3 downto 0)=>PAR_IN(7 downto 4),
  94                    PAR_OUT=>PAR_OUT(1) );
  95         I1 : PARITY_4
  96         Port Map ( PAR_IN(3 downto 0)=>PAR_IN(3 downto 0),
  97                    PAR_OUT=>PAR_OUT(0) );
  98         I10 : PARITY_4
  99         Port Map ( PAR_IN(3 downto 0)=>PAR_OUT(3 downto 0),
 100                    PAR_OUT=>PAR_OUT(9) );
 101
 102 end SCHEMATIC;