5f56b648db4e75f326e303a573f99e099b4a53ed
[raggedstone] / dhwk_old / source / wb_fifo.v
1 module wb_7seg_new (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i,
2 wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, fifo_data_i, fifo_data_o, fifo_we_o, fifo_re_o);
3
4 input clk_i;
5 input nrst_i;
6 input [24:1] wb_adr_i;
7 output [15:0] wb_dat_o;
8 input [15:0] wb_dat_i;
9 input [1:0] wb_sel_i;
10 input wb_we_i;
11 input wb_stb_i;
12 input wb_cyc_i;
13 output wb_ack_o;
14 output wb_err_o;
15 output wb_int_o;
16 input [7:0] fifo_data_i;
17 output [7:0] fifo_data_o;
18 output fifo_we_o;
19 output fifo_re_o;
20
21 reg [15:0] data_reg;
22
23 always @(posedge clk_i or negedge nrst_i)
24 begin
25 if (nrst_i == 0)
26 data_reg <= 16'hABCD;
27 else
28 if (wb_stb_i && wb_we_i)
29 data_reg <= wb_dat_i;
30 end
31
32 assign wb_ack_o = wb_stb_i;
33 assign wb_err_o = 1'b0;
34 assign wb_int_o = 1'b0;
35 assign wb_dat_o = data_reg;
36
37 endmodule
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