610861e05955140afb993f9658dadfe6195bd8b1
[raggedstone] / dhwk / source / reg_io.vhd
1 -- VHDL model created from schematic reg_io.sch -- Jan 09 09:34:12 2007
2
3
4
5 LIBRARY ieee;
6
7 USE ieee.std_logic_1164.ALL;
8 USE ieee.numeric_std.ALL;
9
10
11 entity REG_IO is
12 Port ( AD_REG : In std_logic_vector (31 downto 0);
13 PCI_CLOCK : In std_logic;
14 RESET : In std_logic;
15 WRITE_XX1_0 : In std_logic;
16 WRITE_XX7_6 : In std_logic;
17 REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
18 REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
19 REG_OUT_XX7 : Out std_logic_vector (7 downto 0) );
20 end REG_IO;
21
22 architecture SCHEMATIC of REG_IO is
23
24 SIGNAL gnd : std_logic := '0';
25 SIGNAL vcc : std_logic := '1';
26
27
28 component REG
29 Port ( CLOCK : In std_logic;
30 REG_IN : In std_logic_vector (7 downto 0);
31 RESET : In std_logic;
32 WRITE : In std_logic;
33 REG_OUT : Out std_logic_vector (7 downto 0) );
34 end component;
35
36 begin
37
38 I14 : REG
39 Port Map ( CLOCK=>PCI_CLOCK,
40 REG_IN(7 downto 0)=>AD_REG(7 downto 0), RESET=>RESET,
41 WRITE=>WRITE_XX1_0,
42 REG_OUT(7 downto 0)=>REG_OUT_XX0(7 downto 0) );
43 I15 : REG
44 Port Map ( CLOCK=>PCI_CLOCK,
45 REG_IN(7 downto 0)=>AD_REG(31 downto 24), RESET=>RESET,
46 WRITE=>WRITE_XX7_6,
47 REG_OUT(7 downto 0)=>REG_OUT_XX7(7 downto 0) );
48 I16 : REG
49 Port Map ( CLOCK=>PCI_CLOCK,
50 REG_IN(7 downto 0)=>AD_REG(23 downto 16), RESET=>RESET,
51 WRITE=>WRITE_XX7_6,
52 REG_OUT(7 downto 0)=>REG_OUT_XX6(7 downto 0) );
53
54 end SCHEMATIC;
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