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[raggedstone] / ethernet / source / phydcm.vhd
1 --------------------------------------------------------------------------------
2 -- Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
3 --------------------------------------------------------------------------------
4 -- ____ ____
5 -- / /\/ /
6 -- /___/ \ / Vendor: Xilinx
7 -- \ \ \/ Version : 9.1.02i
8 -- \ \ Application : xaw2vhdl
9 -- / / Filename : phydcm.vhd
10 -- /___/ /\ Timestamp : 03/21/2007 14:56:33
11 -- \ \ / \
12 -- \___\/\___\
13 --
14 --Command: xaw2vhdl-st phydcm.xaw phydcm
15 --Design Name: phydcm
16 --Device: xc3s1500-fg456-4
17 --
18 -- Module phydcm
19 -- Generated by Xilinx Architecture Wizard
20 -- Written for synthesis tool: XST
21
22 library ieee;
23 use ieee.std_logic_1164.ALL;
24 use ieee.numeric_std.ALL;
25 library UNISIM;
26 use UNISIM.Vcomponents.ALL;
27
28 entity phydcm is
29 port ( CLKIN_IN : in std_logic;
30 RST_IN : in std_logic;
31 CLKFX_OUT : out std_logic;
32 CLK0_OUT : out std_logic;
33 LOCKED_OUT : out std_logic);
34 end phydcm;
35
36 architecture BEHAVIORAL of phydcm is
37 signal CLKFB_IN : std_logic;
38 signal CLKFX_BUF : std_logic;
39 signal CLK0_BUF : std_logic;
40 signal GND_BIT : std_logic;
41 component BUFG
42 port ( I : in std_logic;
43 O : out std_logic);
44 end component;
45
46 -- Period Jitter (unit interval) for block DCM_INST = 0.06 UI
47 -- Period Jitter (Peak-to-Peak) for block DCM_INST = 2.27 ns
48 component DCM
49 generic( CLK_FEEDBACK : string := "1X";
50 CLKDV_DIVIDE : real := 2.0;
51 CLKFX_DIVIDE : integer := 1;
52 CLKFX_MULTIPLY : integer := 4;
53 CLKIN_DIVIDE_BY_2 : boolean := FALSE;
54 CLKIN_PERIOD : real := 10.0;
55 CLKOUT_PHASE_SHIFT : string := "NONE";
56 DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
57 DFS_FREQUENCY_MODE : string := "LOW";
58 DLL_FREQUENCY_MODE : string := "LOW";
59 DUTY_CYCLE_CORRECTION : boolean := TRUE;
60 FACTORY_JF : bit_vector := x"C080";
61 PHASE_SHIFT : integer := 0;
62 STARTUP_WAIT : boolean := FALSE;
63 DSS_MODE : string := "NONE");
64 port ( CLKIN : in std_logic;
65 CLKFB : in std_logic;
66 RST : in std_logic;
67 PSEN : in std_logic;
68 PSINCDEC : in std_logic;
69 PSCLK : in std_logic;
70 DSSEN : in std_logic;
71 CLK0 : out std_logic;
72 CLK90 : out std_logic;
73 CLK180 : out std_logic;
74 CLK270 : out std_logic;
75 CLKDV : out std_logic;
76 CLK2X : out std_logic;
77 CLK2X180 : out std_logic;
78 CLKFX : out std_logic;
79 CLKFX180 : out std_logic;
80 STATUS : out std_logic_vector (7 downto 0);
81 LOCKED : out std_logic;
82 PSDONE : out std_logic);
83 end component;
84
85 begin
86 GND_BIT <= '0';
87 CLK0_OUT <= CLKFB_IN;
88 CLKFX_BUFG_INST : BUFG
89 port map (I=>CLKFX_BUF,
90 O=>CLKFX_OUT);
91
92 CLK0_BUFG_INST : BUFG
93 port map (I=>CLK0_BUF,
94 O=>CLKFB_IN);
95
96 DCM_INST : DCM
97 generic map( CLK_FEEDBACK => "1X",
98 CLKDV_DIVIDE => 2.0,
99 CLKFX_DIVIDE => 29,
100 CLKFX_MULTIPLY => 22,
101 CLKIN_DIVIDE_BY_2 => FALSE,
102 CLKIN_PERIOD => 30.303,
103 CLKOUT_PHASE_SHIFT => "NONE",
104 DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
105 DFS_FREQUENCY_MODE => "LOW",
106 DLL_FREQUENCY_MODE => "LOW",
107 DUTY_CYCLE_CORRECTION => TRUE,
108 FACTORY_JF => x"8080",
109 PHASE_SHIFT => 0,
110 STARTUP_WAIT => FALSE)
111 port map (CLKFB=>CLKFB_IN,
112 CLKIN=>CLKIN_IN,
113 DSSEN=>GND_BIT,
114 PSCLK=>GND_BIT,
115 PSEN=>GND_BIT,
116 PSINCDEC=>GND_BIT,
117 RST=>RST_IN,
118 CLKDV=>open,
119 CLKFX=>CLKFX_BUF,
120 CLKFX180=>open,
121 CLK0=>CLK0_BUF,
122 CLK2X=>open,
123 CLK2X180=>open,
124 CLK90=>open,
125 CLK180=>open,
126 CLK270=>open,
127 LOCKED=>LOCKED_OUT,
128 PSDONE=>open,
129 STATUS=>open);
130
131 end BEHAVIORAL;
132
133
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