eth_cop
[raggedstone] / ethernet / source / top.vhd
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 entity ethernet is
5 PORT(
6 PCI_AD : INOUT std_logic_vector(31 downto 0);
7 PCI_CLOCK : IN std_logic;
8 PCI_IDSEL : IN std_logic;
9 PCI_CBEn : INOUT std_logic_vector (3 downto 0);
10 PCI_FRAMEn : INOUT std_logic;
11 PCI_IRDYn : INOUT std_logic;
12 PCI_RSTn : INOUT std_logic;
13 PCI_DEVSELn : INOUT std_logic;
14 PCI_INTAn : INOUT std_logic;
15 PCI_PERRn : INOUT std_logic;
16 PCI_SERRn : INOUT std_logic;
17 PCI_STOPn : INOUT std_logic;
18 PCI_TRDYn : INOUT std_logic;
19 PCI_PAR : INOUT std_logic;
20 PCI_REQn : OUT std_logic;
21 PCI_GNTn : IN std_logic;
22
23 MTX_CLK_PAD_I : IN std_logic;
24 MTXD_PAD_O : OUT std_logic_vector (3 downto 0);
25 MTXEN_PAD_O : OUT std_logic;
26 MRX_CLK_PAD_I : IN std_logic;
27 MRXD_PAD_I : IN std_logic_vector (3 downto 0);
28 MRXDV_PAD_I : IN std_logic;
29 MRXERR_PAD_I : IN std_logic;
30 MCOLL_PAD_I : IN std_logic;
31 MCRS_PAD_I : IN std_logic;
32 MD_PAD_IO : INOUT std_logic;
33 MDC_PAD_O : OUT std_logic;
34
35 LED_2 : OUT std_logic
36 );
37 end ethernet;
38
39 architecture ethernet_arch of ethernet is
40
41 COMPONENT eth_top
42 PORT(
43 wb_clk_i : IN std_logic;
44 wb_rst_i : IN std_logic;
45 wb_dat_i : IN std_logic_vector(31 downto 0);
46 wb_adr_i : IN std_logic_vector(11 downto 2);
47 wb_sel_i : IN std_logic_vector(3 downto 0);
48 wb_we_i : IN std_logic;
49 wb_cyc_i : IN std_logic;
50 wb_stb_i : IN std_logic;
51 m_wb_dat_i : IN std_logic_vector(31 downto 0);
52 m_wb_ack_i : IN std_logic;
53 m_wb_err_i : IN std_logic;
54 mtx_clk_pad_i : IN std_logic;
55 mrx_clk_pad_i : IN std_logic;
56 mrxd_pad_i : IN std_logic_vector(3 downto 0);
57 mrxdv_pad_i : IN std_logic;
58 mrxerr_pad_i : IN std_logic;
59 mcoll_pad_i : IN std_logic;
60 mcrs_pad_i : IN std_logic;
61 md_pad_i : IN std_logic;
62 wb_dat_o : OUT std_logic_vector(31 downto 0);
63 wb_ack_o : OUT std_logic;
64 wb_err_o : OUT std_logic;
65 m_wb_adr_o : OUT std_logic_vector(31 downto 0);
66 m_wb_sel_o : OUT std_logic_vector(3 downto 0);
67 m_wb_we_o : OUT std_logic;
68 m_wb_dat_o : OUT std_logic_vector(31 downto 0);
69 m_wb_cyc_o : OUT std_logic;
70 m_wb_stb_o : OUT std_logic;
71 mtxd_pad_o : OUT std_logic_vector(3 downto 0);
72 mtxen_pad_o : OUT std_logic;
73 mtxerr_pad_o : OUT std_logic;
74 mdc_pad_o : OUT std_logic;
75 md_pad_o : OUT std_logic;
76 md_padoe_o : OUT std_logic;
77 m_wb_cti_o : OUT std_logic_vector(2 downto 0);
78 m_wb_bte_o : OUT std_logic_vector(1 downto 0);
79 int_o : OUT std_logic
80 );
81 END COMPONENT;
82
83 COMPONENT pci_bridge32
84 PORT(
85 wb_clk_i : IN std_logic;
86 wb_rst_i : IN std_logic;
87 wb_int_i : IN std_logic;
88 wbs_adr_i : IN std_logic_vector(31 downto 0);
89 wbs_dat_i : IN std_logic_vector(31 downto 0);
90 wbs_sel_i : IN std_logic_vector(3 downto 0);
91 wbs_cyc_i : IN std_logic;
92 wbs_stb_i : IN std_logic;
93 wbs_we_i : IN std_logic;
94 wbs_cti_i : IN std_logic_vector(2 downto 0);
95 wbs_bte_i : IN std_logic_vector(1 downto 0);
96 wbm_dat_i : IN std_logic_vector(31 downto 0);
97 wbm_ack_i : IN std_logic;
98 wbm_rty_i : IN std_logic;
99 wbm_err_i : IN std_logic;
100 pci_clk_i : IN std_logic;
101 pci_rst_i : IN std_logic;
102 pci_inta_i : IN std_logic;
103 pci_gnt_i : IN std_logic;
104 pci_frame_i : IN std_logic;
105 pci_irdy_i : IN std_logic;
106 pci_idsel_i : IN std_logic;
107 pci_devsel_i : IN std_logic;
108 pci_trdy_i : IN std_logic;
109 pci_stop_i : IN std_logic;
110 pci_ad_i : IN std_logic_vector(31 downto 0);
111 pci_cbe_i : IN std_logic_vector(3 downto 0);
112 pci_par_i : IN std_logic;
113 pci_perr_i : IN std_logic;
114 wb_rst_o : OUT std_logic;
115 wb_int_o : OUT std_logic;
116 wbs_dat_o : OUT std_logic_vector(31 downto 0);
117 wbs_ack_o : OUT std_logic;
118 wbs_rty_o : OUT std_logic;
119 wbs_err_o : OUT std_logic;
120 wbm_adr_o : OUT std_logic_vector(31 downto 0);
121 wbm_dat_o : OUT std_logic_vector(31 downto 0);
122 wbm_sel_o : OUT std_logic_vector(3 downto 0);
123 wbm_cyc_o : OUT std_logic;
124 wbm_stb_o : OUT std_logic;
125 wbm_we_o : OUT std_logic;
126 wbm_cti_o : OUT std_logic_vector(2 downto 0);
127 wbm_bte_o : OUT std_logic_vector(1 downto 0);
128 pci_rst_o : OUT std_logic;
129 pci_inta_o : OUT std_logic;
130 pci_rst_oe_o : OUT std_logic;
131 pci_inta_oe_o : OUT std_logic;
132 pci_req_o : OUT std_logic;
133 pci_req_oe_o : OUT std_logic;
134 pci_frame_o : OUT std_logic;
135 pci_frame_oe_o : OUT std_logic;
136 pci_irdy_oe_o : OUT std_logic;
137 pci_devsel_oe_o : OUT std_logic;
138 pci_trdy_oe_o : OUT std_logic;
139 pci_stop_oe_o : OUT std_logic;
140 pci_ad_oe_o : OUT std_logic_vector(31 downto 0);
141 pci_cbe_oe_o : OUT std_logic_vector(3 downto 0);
142 pci_irdy_o : OUT std_logic;
143 pci_devsel_o : OUT std_logic;
144 pci_trdy_o : OUT std_logic;
145 pci_stop_o : OUT std_logic;
146 pci_ad_o : OUT std_logic_vector(31 downto 0);
147 pci_cbe_o : OUT std_logic_vector(3 downto 0);
148 pci_par_o : OUT std_logic;
149 pci_par_oe_o : OUT std_logic;
150 pci_perr_o : OUT std_logic;
151 pci_perr_oe_o : OUT std_logic;
152 pci_serr_o : OUT std_logic;
153 pci_serr_oe_o : OUT std_logic
154 );
155 END COMPONENT;
156
157 COMPONENT eth_cop
158 PORT(
159 wb_clk_i : IN std_logic;
160 wb_rst_i : IN std_logic;
161 m1_wb_adr_i : IN std_logic_vector(31 downto 0);
162 m1_wb_sel_i : IN std_logic_vector(3 downto 0);
163 m1_wb_we_i : IN std_logic;
164 m1_wb_dat_i : IN std_logic_vector(31 downto 0);
165 m1_wb_cyc_i : IN std_logic;
166 m1_wb_stb_i : IN std_logic;
167 m2_wb_adr_i : IN std_logic_vector(31 downto 0);
168 m2_wb_sel_i : IN std_logic_vector(3 downto 0);
169 m2_wb_we_i : IN std_logic;
170 m2_wb_dat_i : IN std_logic_vector(31 downto 0);
171 m2_wb_cyc_i : IN std_logic;
172 m2_wb_stb_i : IN std_logic;
173 s1_wb_ack_i : IN std_logic;
174 s1_wb_err_i : IN std_logic;
175 s1_wb_dat_i : IN std_logic_vector(31 downto 0);
176 s2_wb_ack_i : IN std_logic;
177 s2_wb_err_i : IN std_logic;
178 s2_wb_dat_i : IN std_logic_vector(31 downto 0);
179 m1_wb_dat_o : OUT std_logic_vector(31 downto 0);
180 m1_wb_ack_o : OUT std_logic;
181 m1_wb_err_o : OUT std_logic;
182 m2_wb_dat_o : OUT std_logic_vector(31 downto 0);
183 m2_wb_ack_o : OUT std_logic;
184 m2_wb_err_o : OUT std_logic;
185 s1_wb_adr_o : OUT std_logic_vector(31 downto 0);
186 s1_wb_sel_o : OUT std_logic_vector(3 downto 0);
187 s1_wb_we_o : OUT std_logic;
188 s1_wb_cyc_o : OUT std_logic;
189 s1_wb_stb_o : OUT std_logic;
190 s1_wb_dat_o : OUT std_logic_vector(31 downto 0);
191 s2_wb_adr_o : OUT std_logic_vector(31 downto 0);
192 s2_wb_sel_o : OUT std_logic_vector(3 downto 0);
193 s2_wb_we_o : OUT std_logic;
194 s2_wb_cyc_o : OUT std_logic;
195 s2_wb_stb_o : OUT std_logic;
196 s2_wb_dat_o : OUT std_logic_vector(31 downto 0)
197 );
198 END COMPONENT;
199
200 signal pci_rst_o : std_logic;
201 signal pci_rst_oe_o : std_logic;
202 signal pci_inta_o : std_logic;
203 signal pci_inta_oe_o : std_logic;
204 signal pci_req_o : std_logic;
205 signal pci_req_oe_o : std_logic;
206 signal pci_frame_o : std_logic;
207 signal pci_frame_oe_o : std_logic;
208 signal pci_irdy_o : std_logic;
209 signal pci_irdy_oe_o : std_logic;
210 signal pci_devsel_o : std_logic;
211 signal pci_devsel_oe_o : std_logic;
212 signal pci_trdy_o : std_logic;
213 signal pci_trdy_oe_o : std_logic;
214 signal pci_stop_o : std_logic;
215 signal pci_stop_oe_o : std_logic;
216 signal pci_par_o : std_logic;
217 signal pci_par_oe_o : std_logic;
218 signal pci_perr_o : std_logic;
219 signal pci_perr_oe_o : std_logic;
220 signal pci_serr_o : std_logic;
221 signal pci_serr_oe_o : std_logic;
222 signal pci_ad_oe_o : std_logic_vector(31 downto 0);
223 signal pci_cbe_oe_o : std_logic_vector(3 downto 0);
224 signal pci_ad_o : std_logic_vector (31 downto 0);
225 signal pci_cbe_o : std_logic_vector (3 downto 0);
226
227 signal wb_clk_i : std_logic;
228 signal wb_rst_i : std_logic;
229 signal wb_dat_i : std_logic_vector (31 downto 0);
230 signal wb_dat_o : std_logic_vector (31 downto 0);
231 signal wb_adr_i : std_logic_vector (11 downto 2);
232 signal wb_sel_i : std_logic_vector (3 downto 0);
233 signal wb_we_i : std_logic;
234 signal wb_cyc_i : std_logic;
235 signal wb_stb_i : std_logic;
236 signal wb_ack_o : std_logic;
237 signal wb_err_o : std_logic;
238 signal m_wb_adr_o : std_logic_vector(31 downto 0);
239 signal m_wb_sel_o : std_logic_vector(3 downto 0);
240 signal m_wb_we_o : std_logic;
241 signal m_wb_dat_o : std_logic_vector(31 downto 0);
242 signal m_wb_dat_i : std_logic_vector(31 downto 0);
243 signal m_wb_cyc_o : std_logic;
244 signal m_wb_stb_o : std_logic;
245 signal m_wb_ack_i : std_logic;
246 signal m_wb_err_i : std_logic;
247 signal md_pad_o : std_logic;
248 signal md_padoe_o : std_logic;
249 signal int_o : std_logic;
250 signal wbm_adr_o : std_logic_vector(31 downto 0);
251
252 signal m_wb_cti_o : std_logic_vector(2 downto 0);
253 signal m_wb_bte_o : std_logic_vector(1 downto 0);
254
255 BEGIN
256
257 PCI_RSTn <= pci_rst_o when (pci_rst_oe_o = '1') else 'Z';
258 PCI_INTAn <= pci_inta_o when (pci_inta_oe_o = '1') else 'Z';
259 PCI_REQn <= pci_req_o when (pci_req_oe_o = '1') else 'Z';
260 PCI_FRAMEn <= pci_frame_o when (pci_frame_oe_o = '1') else 'Z';
261 PCI_IRDYn <= pci_irdy_o when (pci_irdy_oe_o = '1') else 'Z';
262 PCI_DEVSELn <= pci_devsel_o when (pci_devsel_oe_o = '1') else 'Z';
263 PCI_TRDYn <= pci_trdy_o when (pci_trdy_oe_o = '1') else 'Z';
264 PCI_STOPn <= pci_stop_o when (pci_stop_oe_o = '1') else 'Z';
265 PCI_PAR <= pci_par_o when (pci_par_oe_o = '1') else 'Z';
266 PCI_PERRn <= pci_perr_o when (pci_perr_oe_o = '1') else 'Z';
267 PCI_SERRn <= pci_serr_o when (pci_serr_oe_o = '1') else 'Z';
268 MD_PAD_IO <= md_pad_o when (md_padoe_o = '1') else 'Z';
269
270 BLA1: FOR i in 31 downto 0 generate
271 PCI_AD(i) <= pci_ad_o(i) when (pci_ad_oe_o(i) = '1') else 'Z';
272 end generate;
273
274 BLA2: FOR i in 3 downto 0 generate
275 PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z';
276 end generate;
277
278 wb_adr_i <= wbm_adr_o (11 downto 2);
279
280 Inst_pci_bridge32: pci_bridge32 PORT MAP(
281 wb_clk_i => wb_clk_i ,
282 wb_rst_i => '0',
283 wb_rst_o => wb_rst_i,
284 wb_int_i => int_o,
285 -- wb_int_o => ,
286 wbs_adr_i => m_wb_adr_o ,
287 wbs_dat_i => m_wb_dat_o,
288 wbs_dat_o => m_wb_dat_i,
289 wbs_sel_i => m_wb_sel_o,
290 wbs_cyc_i => m_wb_cyc_o,
291 wbs_stb_i => m_wb_stb_o,
292 wbs_we_i => m_wb_we_o,
293 wbs_cti_i => m_wb_cti_o,
294 wbs_bte_i => m_wb_bte_o,
295 wbs_ack_o => m_wb_ack_i,
296 -- wbs_rty_o => ,
297 wbs_err_o => m_wb_err_i,
298 wbm_adr_o => wbm_adr_o,
299 wbm_dat_i => wb_dat_o,
300 wbm_dat_o => wb_dat_i,
301 wbm_sel_o => wb_sel_i,
302 wbm_cyc_o => wb_cyc_i,
303 wbm_stb_o => wb_stb_i,
304 wbm_we_o => wb_we_i,
305 -- wbm_cti_o => ,
306 -- wbm_bte_o => ,
307 wbm_ack_i => wb_ack_o ,
308 wbm_rty_i => '0',
309 wbm_err_i => wb_err_o,
310 pci_clk_i => PCI_CLOCK,
311 pci_rst_i => PCI_RSTn,
312 pci_rst_o => pci_rst_o ,
313 pci_rst_oe_o => pci_rst_oe_o,
314 pci_inta_i => PCI_INTAn,
315 pci_inta_o => pci_inta_o,
316 pci_inta_oe_o => pci_inta_oe_o,
317 pci_req_o => pci_req_o,
318 pci_req_oe_o => pci_req_oe_o,
319 pci_gnt_i => PCI_GNTn,
320 pci_frame_i => PCI_FRAMEn,
321 pci_frame_o => pci_frame_o,
322 pci_frame_oe_o => pci_frame_oe_o,
323 pci_irdy_oe_o => pci_irdy_oe_o,
324 pci_devsel_oe_o => pci_devsel_oe_o,
325 pci_trdy_oe_o => pci_trdy_oe_o,
326 pci_stop_oe_o => pci_stop_oe_o,
327 pci_ad_oe_o => pci_ad_oe_o,
328 pci_cbe_oe_o => pci_cbe_oe_o,
329 pci_irdy_i => PCI_IRDYn,
330 pci_irdy_o => pci_irdy_o,
331 pci_idsel_i => PCI_IDSEL,
332 pci_devsel_i => PCI_DEVSELn,
333 pci_devsel_o => pci_devsel_o,
334 pci_trdy_i => PCI_TRDYn,
335 pci_trdy_o => pci_trdy_o,
336 pci_stop_i => PCI_STOPn,
337 pci_stop_o => pci_stop_o,
338 pci_ad_i => PCI_AD,
339 pci_ad_o => pci_ad_o,
340 pci_cbe_i => PCI_CBEn,
341 pci_cbe_o => pci_cbe_o,
342 pci_par_i => PCI_PAR,
343 pci_par_o => pci_par_o,
344 pci_par_oe_o => pci_par_oe_o,
345 pci_perr_i => PCI_PERRn,
346 pci_perr_o => pci_perr_o,
347 pci_perr_oe_o => pci_perr_oe_o,
348 pci_serr_o => pci_serr_o,
349 pci_serr_oe_o => pci_serr_oe_o
350 );
351
352 Inst_eth_top: eth_top PORT MAP(
353 wb_clk_i => wb_clk_i ,
354 wb_rst_i => wb_rst_i ,
355 wb_dat_i => wb_dat_i ,
356 wb_dat_o => wb_dat_o ,
357 wb_adr_i => wb_adr_i ,
358 wb_sel_i => wb_sel_i ,
359 wb_we_i => wb_we_i ,
360 wb_cyc_i => wb_cyc_i ,
361 wb_stb_i => wb_stb_i ,
362 wb_ack_o => wb_ack_o ,
363 wb_err_o => wb_err_o ,
364 m_wb_adr_o => m_wb_adr_o,
365 m_wb_sel_o => m_wb_sel_o,
366 m_wb_we_o => m_wb_we_o ,
367 m_wb_dat_o => m_wb_dat_o,
368 m_wb_dat_i => m_wb_dat_i,
369 m_wb_cyc_o => m_wb_cyc_o,
370 m_wb_stb_o => m_wb_stb_o,
371 m_wb_ack_i => m_wb_ack_i,
372 m_wb_err_i => m_wb_err_i,
373 mtx_clk_pad_i => MTX_CLK_PAD_I,
374 mtxd_pad_o => MTXD_PAD_O,
375 mtxen_pad_o => MTXEN_PAD_O,
376 mtxerr_pad_o => LED_2,
377 mrx_clk_pad_i => MRX_CLK_PAD_I,
378 mrxd_pad_i => MRXD_PAD_I,
379 mrxdv_pad_i => MRXDV_PAD_I,
380 mrxerr_pad_i => MRXERR_PAD_I,
381 mcoll_pad_i => MCOLL_PAD_I,
382 mcrs_pad_i => MCRS_PAD_I,
383 mdc_pad_o => MDC_PAD_O,
384 md_pad_i => MD_PAD_IO,
385 md_pad_o => md_pad_o,
386 md_padoe_o => md_padoe_o,
387 m_wb_cti_o => m_wb_cti_o,
388 m_wb_bte_o => m_wb_bte_o,
389 int_o => int_o
390 );
391
392 --Inst_eth_cop: eth_cop PORT MAP(
393 -- wb_clk_i => ,
394 -- wb_rst_i => ,
395 -- m1_wb_adr_i => ,
396 -- m1_wb_sel_i => ,
397 -- m1_wb_we_i => ,
398 -- m1_wb_dat_o => ,
399 -- m1_wb_dat_i => ,
400 -- m1_wb_cyc_i => ,
401 -- m1_wb_stb_i => ,
402 -- m1_wb_ack_o => ,
403 -- m1_wb_err_o => ,
404 -- m2_wb_adr_i => ,
405 -- m2_wb_sel_i => ,
406 -- m2_wb_we_i => ,
407 -- m2_wb_dat_o => ,
408 -- m2_wb_dat_i => ,
409 -- m2_wb_cyc_i => ,
410 -- m2_wb_stb_i => ,
411 -- m2_wb_ack_o => ,
412 -- m2_wb_err_o => ,
413 -- s1_wb_adr_o => ,
414 -- s1_wb_sel_o => ,
415 -- s1_wb_we_o => ,
416 -- s1_wb_cyc_o => ,
417 -- s1_wb_stb_o => ,
418 -- s1_wb_ack_i => ,
419 -- s1_wb_err_i => ,
420 -- s1_wb_dat_i => ,
421 -- s1_wb_dat_o => ,
422 -- s2_wb_adr_o => ,
423 -- s2_wb_sel_o => ,
424 -- s2_wb_we_o => ,
425 -- s2_wb_cyc_o => ,
426 -- s2_wb_stb_o => ,
427 -- s2_wb_ack_i => ,
428 -- s2_wb_err_i => ,
429 -- s2_wb_dat_i => ,
430 -- s2_wb_dat_o =>
431 --);
432
433 end architecture ethernet_arch;
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