git.zerfleddert.de Git - raggedstone/blob - dhwk/source/pci/config_wr_0.vhd

   1 -- J.STELZNER
   2 -- INFORMATIK-3 LABOR
   3 -- 23.08.2006
   4 -- File: CONFIG_WR_0.VHD
   5
   6 library IEEE;
   7 use IEEE.std_logic_1164.all;
   8
   9 entity CONFIG_WR_0 is
  10         port
  11         (
  12                 ADDR_REG :in std_logic_vector(31 downto 0);
  13                 CF_WR_COM :in std_logic;
  14                 IRDY_REGn :in std_logic;
  15                 TRDYn :in std_logic;
  16                 CONF_WR_04H :out std_logic;
  17                 CONF_WR_10H :out std_logic;
  18                 CONF_WR_3CH :out std_logic
  19                 --CONF_WR_40H :out std_logic
  20         );
  21 end entity CONFIG_WR_0;
  22
  23 architecture CONFIG_WR_0_DESIGN of CONFIG_WR_0 is
  24
  25  --
  26  --
  27  --
  28  --
  29  --
  30  -- PCI Configuration Space Header
  31  --
  32  -- \ Bit
  33  -- \
  34  --Address |31 24|23 16|15 8|7 0|
  35  -----------------------------------------------------------------
  36  --00 |Device ID |Vendor ID |
  37  --04 |Status |Command |
  38  --08 |Class Code |Revision ID |
  39  --0C |BIST |Header Type |Latency T. |Cache L.S. |
  40  --10-24 |Base Address Register |
  41  --28 |Cardbus CIS Pointer |
  42  --2C |Subsystem ID |Subsystem Vendor ID |
  43  --30 |Expansion ROM Base Address |
  44  --34 |Reserved |
  45  --38 |Reserved |
  46  --3C |Max_Lat |Min_Gnt |Int_Pin |Int_Line |
  47  --40-FF | |
  48  -----------------------------------------------------------------
  49
  50
  51  --PCI Bus Commands
  52  --C/BE[3..0] Command Type
  53  --------------------------------------
  54  -- 0000 Interrupt Acknowledge
  55  -- 0001 Special Cycle
  56  -- 0010 I/O Read
  57  -- 0011 I/O Write
  58  -- 0100 Reserved
  59  -- 0101 Reserved
  60  -- 0110 Memory Read
  61  -- 0111 Memory Write
  62  --
  63  -- 1000 Reserved
  64  -- 1001 Reserved
  65  -- 1010 Configuration Read
  66  -- 1011 Configuration Write
  67  -- 1100 Memory Read Multiple
  68  -- 1101 Dual Address Cycle
  69  -- 1110 Memory Read Line
  70  -- 1111 Memory Write and Invalidate
  71
  72
  73  --PCI Byte Enable
  74  --C/BE[3..0] gueltige Datenbits
  75  -------------------------------
  76  -- 0000 AD 31..0
  77  -- 1000 AD 23..0
  78  -- 1100 AD 15..0
  79  -- 1110 AD 7..0
  80
  81         constant CMD_INT_ACK :std_logic_vector(3 downto 0) := "0000";
  82         constant CMD_SP_CYC :std_logic_vector(3 downto 0) := "0001";
  83         constant CMD_IO_READ :std_logic_vector(3 downto 0) := "0010";
  84         constant CMD_IO_WRITE :std_logic_vector(3 downto 0) := "0011";
  85         constant CMD_RES_4 :std_logic_vector(3 downto 0) := "0100";
  86         constant CMD_RES_5 :std_logic_vector(3 downto 0) := "0101";
  87         constant CMD_MEM_READ :std_logic_vector(3 downto 0) := "0110";
  88         constant CMD_MEM_WRITE :std_logic_vector(3 downto 0) := "0111";
  89         constant CMD_RES_8 :std_logic_vector(3 downto 0) := "1000";
  90         constant CMD_RES_9 :std_logic_vector(3 downto 0) := "1001";
  91         constant CMD_CONF_READ :std_logic_vector(3 downto 0) := "1010";
  92         constant CMD_CONF_WRITE :std_logic_vector(3 downto 0) := "1011";
  93         constant CMD_MEM_READ_M :std_logic_vector(3 downto 0) := "1100";
  94         constant CMD_DU_ADR_CYC :std_logic_vector(3 downto 0) := "1101";
  95         constant CMD_MEN_READ_L :std_logic_vector(3 downto 0) := "1110";
  96         constant CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";
  97
  98         signal CONFIG_ADDR :std_logic_vector(7 downto 0);
  99         signal CONFIG_WRITE :std_logic_vector(3 downto 0);
 100
 101
 102 begin
 103
 104  --*******************************************************************
 105  --******************* PCI Write Configuration Address ***************
 106  --*******************************************************************
 107
 108         CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);
 109
 110
 111         process (CF_WR_COM,IRDY_REGn,TRDYn,CONFIG_ADDR)
 112         begin
 113
 114                 if CF_WR_COM = '1' and IRDY_REGn = '0' and TRDYn = '0' then
 115
 116                         if CONFIG_ADDR = X"04" then
 117                                 CONFIG_WRITE <= "0001";
 118
 119                         elsif CONFIG_ADDR = X"10" then
 120                                 CONFIG_WRITE <= "0010";
 121
 122                         elsif CONFIG_ADDR = X"3C" then
 123                                 CONFIG_WRITE <= "0100";
 124
 125                         -- elsif CONFIG_ADDR = X"40" then
 126                         --         CONFIG_WRITE <= "1000";
 127                         else
 128                                 CONFIG_WRITE <= "0000";
 129                         end if;
 130                 else
 131                         CONFIG_WRITE <= "0000";
 132                 end if;
 133         end process;
 134
 135         CONF_WR_04H <= CONFIG_WRITE(0);
 136         CONF_WR_10H <= CONFIG_WRITE(1);
 137         CONF_WR_3CH <= CONFIG_WRITE(2);
 138         --CONF_WR_40H <= CONFIG_WRITE(3);
 139
 140 end architecture CONFIG_WR_0_DESIGN;