git.zerfleddert.de Git - raggedstone/blob - dhwk/source/pci/config_space_header.vhd

   1 LIBRARY ieee;
   2
   3 USE ieee.std_logic_1164.ALL;
   4 USE ieee.numeric_std.ALL;
   5
   6
   7 entity CONFIG_SPACE_HEADER is
   8         Port ( AD_REG : In std_logic_vector (31 downto 0);
   9                ADDR_REG : In std_logic_vector (31 downto 0);
  10                CBE_REGn : In std_logic_vector (3 downto 0);
  11                CF_RD_COM : In std_logic;
  12                CF_WR_COM : In std_logic;
  13                IRDY_REGn : In std_logic;
  14                PCI_CLOCK : In std_logic;
  15                PCI_RSTn : In std_logic;
  16                PERR : In std_logic;
  17                REVISION_ID : In std_logic_vector (7 downto 0);
  18                SERR : In std_logic;
  19                TRDYn : In std_logic;
  20                VENDOR_ID : In std_logic_vector (15 downto 0);
  21                CONF_DATA : Out std_logic_vector (31 downto 0);
  22                CONF_DATA_04H : Out std_logic_vector (31 downto 0);
  23                CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
  24 end CONFIG_SPACE_HEADER;
  25
  26 architecture SCHEMATIC of CONFIG_SPACE_HEADER is
  27
  28         constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE";
  29         --other comm. device
  30         constant CONF_CLASS_CODE :std_logic_vector (31 downto 8) := X"078000";
  31
  32         signal CONF_MAX_LAT :std_logic_vector (31 downto 24);
  33         signal CONF_MIN_GNT :std_logic_vector (23 downto 16);
  34         signal CONF_INT_PIN :std_logic_vector (15 downto 8);
  35         signal CONF_INT_LINE :std_logic_vector ( 7 downto 0);
  36
  37         signal CONF_BAS_ADDR_REG :std_logic_vector(31 downto 0);
  38
  39         signal CONF_STATUS :std_logic_vector(31 downto 16);
  40         signal CONF_COMMAND :std_logic_vector(15 downto 0);
  41
  42         -- PCI Configuration Space Header
  43         --
  44         -- \ Bit
  45         -- \
  46         --Address |31 24|23 16|15 8|7 0|
  47         -----------------------------------------------------------------
  48         --00 |Device ID |Vendor ID |
  49         --04 |Status |Command |
  50         --08 |Class Code |Revision ID |
  51         --0C |BIST |Header Type |Latency T. |Cache L.S. |
  52         --10-24 |Base Address Register |
  53         --28 |Cardbus CIS Pointer |
  54         --2C |Subsystem ID |Subsystem Vendor ID |
  55         --30 |Expansion ROM Base Address |
  56         --34 |Reserved |
  57         --38 |Reserved |
  58         --3C |Max_Lat |Min_Gnt |Int_Pin |Int_Line |
  59         --40-FF | |
  60         -----------------------------------------------------------------
  61
  62
  63         --PCI Bus Commands
  64         --C/BE[3..0] Command Type
  65         --------------------------------------
  66         -- 0000 Interrupt Acknowledge
  67         -- 0001 Special Cycle
  68         -- 0010 I/O Read
  69         -- 0011 I/O Write
  70         -- 0100 Reserved
  71         -- 0101 Reserved
  72         -- 0110 Memory Read
  73         -- 0111 Memory Write
  74         --
  75         -- 1000 Reserved
  76         -- 1001 Reserved
  77         -- 1010 Configuration Read
  78         -- 1011 Configuration Write
  79         -- 1100 Memory Read Multiple
  80         -- 1101 Dual Address Cycle
  81         -- 1110 Memory Read Line
  82         -- 1111 Memory Write and Invalidate
  83
  84
  85         --PCI Byte Enable
  86         --C/BE[3..0] gueltige Datenbits
  87         -------------------------------
  88         -- 0000 AD 31..0
  89         -- 1000 AD 23..0
  90         -- 1100 AD 15..0
  91         -- 1110 AD 7..0
  92
  93         constant CMD_INT_ACK :std_logic_vector(3 downto 0) := "0000";
  94         constant CMD_SP_CYC :std_logic_vector(3 downto 0) := "0001";
  95         constant CMD_IO_READ :std_logic_vector(3 downto 0) := "0010";
  96         constant CMD_IO_WRITE :std_logic_vector(3 downto 0) := "0011";
  97         constant CMD_RES_4 :std_logic_vector(3 downto 0) := "0100";
  98         constant CMD_RES_5 :std_logic_vector(3 downto 0) := "0101";
  99         constant CMD_MEM_READ :std_logic_vector(3 downto 0) := "0110";
 100         constant CMD_MEM_WRITE :std_logic_vector(3 downto 0) := "0111";
 101         constant CMD_RES_8 :std_logic_vector(3 downto 0) := "1000";
 102         constant CMD_RES_9 :std_logic_vector(3 downto 0) := "1001";
 103         constant CMD_CONF_READ :std_logic_vector(3 downto 0) := "1010";
 104         constant CMD_CONF_WRITE :std_logic_vector(3 downto 0) := "1011";
 105         constant CMD_MEM_READ_M :std_logic_vector(3 downto 0) := "1100";
 106         constant CMD_DU_ADR_CYC :std_logic_vector(3 downto 0) := "1101";
 107         constant CMD_MEN_READ_L :std_logic_vector(3 downto 0) := "1110";
 108         constant CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";
 109
 110         signal CONFIG_ADDR :std_logic_vector(7 downto 0);
 111         signal CONFIG_WRITE :std_logic_vector(3 downto 0);
 112
 113         SIGNAL gnd : std_logic := '0';
 114         SIGNAL vcc : std_logic := '1';
 115
 116         signal CONF_WR_04H : std_logic;
 117         signal CONF_WR_10H : std_logic;
 118         signal CONF_WR_3CH : std_logic;
 119         signal CONF_READ_SEL : std_logic_vector (2 downto 0);
 120         signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
 121         signal CONF_DATA_08H : std_logic_vector (31 downto 0);
 122         signal CONF_DATA_00H : std_logic_vector (31 downto 0);
 123
 124 begin
 125         CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;
 126         CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;
 127         CONF_DATA_04H <= CONF_STATUS & CONF_COMMAND;
 128
 129         CONF_MAX_LAT <= X"00";
 130         CONF_MIN_GNT <= X"00";
 131         -- CONF_INT_PIN <= X"00"; -- Interrupt -
 132         CONF_INT_PIN <= X"01"; -- Interrupt A
 133         -- CONF_INT_PIN <= X"02"; -- Interrupt B
 134         -- CONF_INT_PIN <= X"03"; -- Interrupt C
 135         -- CONF_INT_PIN <= X"04"; -- Interrupt D
 136         -- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert
 137         CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;
 138
 139         CONF_BAS_ADDR_REG(1 downto 0) <= "01";-- Base Address Register for "I/O"
 140         CONF_BAS_ADDR_REG(3 downto 2) <= "00";-- IO Bereich = 16 BYTE
 141         CONF_DATA_10H <= CONF_BAS_ADDR_REG;
 142
 143         process (PCI_CLOCK,PCI_RSTn)
 144         begin
 145         if PCI_RSTn = '0' then
 146                 CONF_INT_LINE <= (others => '0');
 147
 148         elsif (rising_edge(PCI_CLOCK)) then
 149                 if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then
 150                         CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
 151                 end if;
 152         end if;
 153         end process;
 154
 155         process (PCI_CLOCK,PCI_RSTn)
 156         begin
 157
 158         -- if PCI_RSTn = '0' then CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0');
 159         if PCI_RSTn = '0' then
 160                 CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0');
 161
 162         elsif (rising_edge(PCI_CLOCK)) then
 163
 164                 if CONF_WR_10H = '1'and CBE_REGn(3) = '0' then
 165                         CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24);
 166                 else
 167                         CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24);
 168                 end if;
 169
 170                 if CONF_WR_10H = '1'and CBE_REGn(2) = '0' then
 171                         CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16);
 172                 else
 173                         CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16);
 174                 end if;
 175
 176                 if CONF_WR_10H = '1'and CBE_REGn(1) = '0' then
 177                         CONF_BAS_ADDR_REG(15 downto 8) <= AD_REG(15 downto 8);
 178                 else
 179                         CONF_BAS_ADDR_REG(15 downto 8) <= CONF_BAS_ADDR_REG(15 downto 8);
 180                 end if;
 181
 182                 -- if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
 183                 --         CONF_BAS_ADDR_REG( 7 downto 2) <= AD_REG( 7 downto 2);
 184                 -- else
 185                 --         CONF_BAS_ADDR_REG( 7 downto 2) <= CONF_BAS_ADDR_REG( 7 downto 2);
 186                 -- end if;
 187
 188                 if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
 189                         CONF_BAS_ADDR_REG( 7 downto 4) <= AD_REG( 7 downto 4);
 190                 else
 191                         CONF_BAS_ADDR_REG( 7 downto 4) <= CONF_BAS_ADDR_REG( 7 downto 4);
 192                 end if;
 193         end if;
 194         end process;
 195
 196         --*******************************************************************
 197         --************* PCI Configuration Space Header "STATUS" *************
 198         --*******************************************************************
 199
 200         CONF_STATUS(20 downto 16) <= "00000";-- Reserved
 201         CONF_STATUS(21 ) <= '0';-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz
 202         CONF_STATUS(22 ) <= '0';-- MAS/TAR: "R_O"
 203         CONF_STATUS(23 ) <= '0';-- ???/???: "R_O" : fast back-to-back
 204         CONF_STATUS(24 ) <= '0';-- Master :
 205         --CONF_STATUS(26 downto 25) <= "00";-- Mas/Tar: "R_O" : timing fast for "DEVSEL"
 206         CONF_STATUS(26 downto 25) <= "01";-- Mas/Tar: "R_O" : timing medium for "DEVSEL"
 207         --CONF_STATUS(26 downto 25) <= "10";-- Mas/Tar: "R_O" : timing slow for "DEVSEL"
 208         --CONF_STATUS(26 downto 25) <= "11";-- Mas/Tar: "R_O" : reserved
 209         CONF_STATUS(27 ) <= '0';-- Target : "R_W" : Taget-Abort
 210         CONF_STATUS(28 ) <= '0';-- Master : "R_W" : Taget-Abort
 211         CONF_STATUS(29 ) <= '0';-- Master : "R_W" : Master-Abort
 212         --CONF_STATUS(30 ) <= SERR;-- Mas/Tar: "R_W" : SERR
 213         --CONF_STATUS(31 ) <= PERR;-- Mas/Tar: "R_W" : PERR
 214
 215         process (PCI_CLOCK,PCI_RSTn)
 216         begin
 217         if PCI_RSTn = '0' then
 218                 CONF_STATUS(30) <= '0';
 219                 CONF_STATUS(31) <= '0';
 220
 221         elsif (rising_edge(PCI_CLOCK)) then
 222                 if CONF_WR_04H = '1' and CBE_REGn(3) = '0' then
 223                         CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30));
 224                         CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31));
 225
 226                 else
 227                         CONF_STATUS(30) <= SERR or CONF_STATUS(30);
 228                         CONF_STATUS(31) <= PERR or CONF_STATUS(31);
 229
 230                 end if;
 231         end if;
 232         end process;
 233
 234         --*******************************************************************
 235         --*********** PCI Configuration Space Header "COMMAND" **************
 236         --*******************************************************************
 237
 238         -- CONF_COMMAND( 0) <= '0';-- I/O Space accesses ???
 239         -- CONF_COMMAND( 1) <= '0';-- Mem Space accesses ???
 240         -- CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus
 241         -- CONF_COMMAND( 3) <= '0';-- Special Cycle ???
 242         -- CONF_COMMAND( 4) <= '0';-- Master ???
 243         -- CONF_COMMAND( 5) <= '0';-- VGA ???
 244         -- CONF_COMMAND( 6) <= '0';-- Party checking enable/disable
 245         CONF_COMMAND( 7) <= '0';-- address/data stepping ???
 246         -- CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn"
 247         -- CONF_COMMAND( 9) <= '0';-- fast back-to-back
 248         -- CONF_COMMAND(10) <= '0';-- Reserved
 249         -- CONF_COMMAND(11) <= '0';-- Reserved
 250         -- CONF_COMMAND(12) <= '0';-- Reserved
 251         -- CONF_COMMAND(13) <= '0';-- Reserved
 252         -- CONF_COMMAND(14) <= '0';-- Reserved
 253         -- CONF_COMMAND(15) <= '0';-- Reserved
 254
 255         process (PCI_CLOCK,PCI_RSTn)
 256         begin
 257                 if PCI_RSTn = '0' then
 258                         CONF_COMMAND(15 downto 8) <= (others =>'0');
 259                         CONF_COMMAND( 6 downto 0) <= (others =>'0');
 260
 261                 elsif (rising_edge(PCI_CLOCK)) then
 262
 263                         if CONF_WR_04H = '1'and CBE_REGn(1) = '0' then
 264                                 CONF_COMMAND(15 downto 8) <= AD_REG(15 downto 8);
 265                         else
 266                                 CONF_COMMAND(15 downto 8) <= CONF_COMMAND(15 downto 8);
 267                         end if;
 268
 269                         if CONF_WR_04H = '1'and CBE_REGn(0) = '0' then
 270                                 CONF_COMMAND( 6 downto 0) <= AD_REG( 6 downto 0);
 271                         else
 272                                 CONF_COMMAND( 6 downto 0) <= CONF_COMMAND( 6 downto 0);
 273                         end if;
 274                 end if;
 275         end process;
 276
 277
 278         --*******************************************************************
 279         --******************* PCI Write Configuration Address ***************
 280         --*******************************************************************
 281
 282         CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);
 283
 284
 285         process (CF_WR_COM,IRDY_REGn,TRDYn,CONFIG_ADDR)
 286         begin
 287
 288                 if CF_WR_COM = '1' and IRDY_REGn = '0' and TRDYn = '0' then
 289
 290                         if CONFIG_ADDR = X"04" then
 291                                 CONFIG_WRITE <= "0001";
 292
 293                         elsif CONFIG_ADDR = X"10" then
 294                                 CONFIG_WRITE <= "0010";
 295
 296                         elsif CONFIG_ADDR = X"3C" then
 297                                 CONFIG_WRITE <= "0100";
 298
 299                         -- elsif CONFIG_ADDR = X"40" then
 300                         --         CONFIG_WRITE <= "1000";
 301                         else
 302                                 CONFIG_WRITE <= "0000";
 303                         end if;
 304                 else
 305                         CONFIG_WRITE <= "0000";
 306                 end if;
 307         end process;
 308
 309         CONF_WR_04H <= CONFIG_WRITE(0);
 310         CONF_WR_10H <= CONFIG_WRITE(1);
 311         CONF_WR_3CH <= CONFIG_WRITE(2);
 312         --CONF_WR_40H <= CONFIG_WRITE(3);
 313
 314         process (CF_RD_COM, CONFIG_ADDR)
 315         begin
 316
 317                 if CF_RD_COM = '1' then
 318                         if CONFIG_ADDR = X"00" then
 319                                 CONF_READ_SEL <= "000";
 320
 321                         elsif CONFIG_ADDR = X"04" then
 322                                 CONF_READ_SEL <= "001";
 323
 324                         elsif CONFIG_ADDR = X"08" then
 325                                 CONF_READ_SEL <= "010";
 326
 327                         elsif CONFIG_ADDR = X"10" then
 328                                 CONF_READ_SEL <= "011";
 329
 330                         elsif CONFIG_ADDR = X"3C" then
 331                                 CONF_READ_SEL <= "100";
 332
 333                         elsif CONFIG_ADDR = X"40" then
 334                                 CONF_READ_SEL <= "101";
 335
 336                         else
 337                                 CONF_READ_SEL <= "111";
 338                         end if;
 339                 else
 340                         CONF_READ_SEL <= "111";
 341                 end if;
 342         end process;
 343
 344 end SCHEMATIC;