EDK project
[raggedstone] / xps / raggedstone.mhs
1 # ##############################################################################
2 # Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4
3 # Thu Mar 22 21:42:23 2007
4 # Target Board: Custom
5 # Family: spartan3
6 # Device: xc3s1500
7 # Package: fg456
8 # Speed Grade: -4
9 # Processor: Microblaze
10 # System clock frequency: 50.000000 MHz
11 # Debug interface: On-Chip HW Debug Module
12 # On Chip Memory : 64 KB
13 # ##############################################################################
14
15
16 PARAMETER VERSION = 2.1.0
17
18
19 PORT fpga_0_RS232_req_to_send_pin = net_gnd, DIR = O
20 PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I
21 PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O
22 PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
23 PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
24 PORT RS232foff = net_vcc, DIR = O
25 PORT LED_out = GPIO_LED_out, VEC = [0:3], DIR = O
26 PORT MEM_FLASH_DQ = FLASH_DQ, DIR = IO, VEC = [7:0]
27 PORT MEM_FLASH_ADDR = FLASH_ADDR, DIR = O, VEC = [18:0]
28 PORT MEM_FLASH_CE = FLASH_CEN, DIR = O, VEC = [0:0]
29 PORT MEM_FLASH_OE = FLASH_OEN, DIR = O, VEC = [0:0]
30 PORT MEM_FLASH_WE = FLASH_WEN, DIR = O
31 PORT SEVENSEG_out = GPIO_7SEG_OUT, DIR = O, VEC = [0:12]
32 PORT DBG_FLASH_ADDR = FLASH_ADDR_split, DIR = O, VEC = [0:31]
33
34
35 BEGIN microblaze
36 PARAMETER INSTANCE = microblaze_0
37 PARAMETER HW_VER = 4.00.b
38 PARAMETER C_USE_FPU = 0
39 PARAMETER C_DEBUG_ENABLED = 1
40 PARAMETER C_NUMBER_OF_PC_BRK = 2
41 PARAMETER C_FSL_DATA_SIZE = 32
42 PARAMETER C_NUMBER_OF_RD_ADDR_BRK = 0
43 PARAMETER C_NUMBER_OF_WR_ADDR_BRK = 0
44 BUS_INTERFACE DLMB = dlmb
45 BUS_INTERFACE ILMB = ilmb
46 BUS_INTERFACE DOPB = mb_opb
47 BUS_INTERFACE IOPB = mb_opb
48 PORT DBG_CAPTURE = DBG_CAPTURE_s
49 PORT DBG_CLK = DBG_CLK_s
50 PORT DBG_REG_EN = DBG_REG_EN_s
51 PORT DBG_TDI = DBG_TDI_s
52 PORT DBG_TDO = DBG_TDO_s
53 PORT DBG_UPDATE = DBG_UPDATE_s
54 END
55
56 BEGIN opb_v20
57 PARAMETER INSTANCE = mb_opb
58 PARAMETER HW_VER = 1.10.c
59 PARAMETER C_EXT_RESET_HIGH = 0
60 PORT SYS_Rst = sys_rst_s
61 PORT OPB_Clk = sys_clk_s
62 END
63
64 BEGIN opb_mdm
65 PARAMETER INSTANCE = debug_module
66 PARAMETER HW_VER = 2.00.a
67 PARAMETER C_MB_DBG_PORTS = 1
68 PARAMETER C_USE_UART = 0
69 PARAMETER C_BASEADDR = 0x41400000
70 PARAMETER C_HIGHADDR = 0x4140ffff
71 BUS_INTERFACE SOPB = mb_opb
72 PORT DBG_CAPTURE_0 = DBG_CAPTURE_s
73 PORT DBG_CLK_0 = DBG_CLK_s
74 PORT DBG_REG_EN_0 = DBG_REG_EN_s
75 PORT DBG_TDI_0 = DBG_TDI_s
76 PORT DBG_TDO_0 = DBG_TDO_s
77 PORT DBG_UPDATE_0 = DBG_UPDATE_s
78 END
79
80 BEGIN lmb_v10
81 PARAMETER INSTANCE = ilmb
82 PARAMETER HW_VER = 1.00.a
83 PARAMETER C_EXT_RESET_HIGH = 0
84 PORT SYS_Rst = sys_rst_s
85 PORT LMB_Clk = sys_clk_s
86 END
87
88 BEGIN lmb_v10
89 PARAMETER INSTANCE = dlmb
90 PARAMETER HW_VER = 1.00.a
91 PARAMETER C_EXT_RESET_HIGH = 0
92 PORT SYS_Rst = sys_rst_s
93 PORT LMB_Clk = sys_clk_s
94 END
95
96 BEGIN lmb_bram_if_cntlr
97 PARAMETER INSTANCE = dlmb_cntlr
98 PARAMETER HW_VER = 1.00.b
99 PARAMETER C_BASEADDR = 0x00000000
100 PARAMETER C_HIGHADDR = 0x00007FFF
101 BUS_INTERFACE SLMB = dlmb
102 BUS_INTERFACE BRAM_PORT = dlmb_port
103 END
104
105 BEGIN lmb_bram_if_cntlr
106 PARAMETER INSTANCE = ilmb_cntlr
107 PARAMETER HW_VER = 1.00.b
108 PARAMETER C_BASEADDR = 0x00000000
109 PARAMETER C_HIGHADDR = 0x00007FFF
110 BUS_INTERFACE SLMB = ilmb
111 BUS_INTERFACE BRAM_PORT = ilmb_port
112 END
113
114 BEGIN bram_block
115 PARAMETER INSTANCE = lmb_bram
116 PARAMETER HW_VER = 1.00.a
117 BUS_INTERFACE PORTA = ilmb_port
118 BUS_INTERFACE PORTB = dlmb_port
119 END
120
121 BEGIN opb_uartlite
122 PARAMETER INSTANCE = RS232
123 PARAMETER HW_VER = 1.00.b
124 PARAMETER C_BAUDRATE = 115200
125 PARAMETER C_DATA_BITS = 8
126 PARAMETER C_ODD_PARITY = 1
127 PARAMETER C_USE_PARITY = 0
128 PARAMETER C_CLK_FREQ = 50000000
129 PARAMETER C_BASEADDR = 0x40600000
130 PARAMETER C_HIGHADDR = 0x4060ffff
131 BUS_INTERFACE SOPB = mb_opb
132 PORT RX = fpga_0_RS232_RX
133 PORT TX = fpga_0_RS232_TX
134 END
135
136 BEGIN dcm_module
137 PARAMETER INSTANCE = dcm_0
138 PARAMETER HW_VER = 1.00.a
139 PARAMETER C_CLK0_BUF = TRUE
140 PARAMETER C_CLKIN_PERIOD = 20.000000
141 PARAMETER C_CLK_FEEDBACK = 1X
142 PARAMETER C_DLL_FREQUENCY_MODE = LOW
143 PARAMETER C_EXT_RESET_HIGH = 1
144 PORT CLKIN = dcm_clk_s
145 PORT CLK0 = sys_clk_s
146 PORT CLKFB = sys_clk_s
147 PORT RST = net_gnd
148 PORT LOCKED = dcm_0_lock
149 END
150
151 BEGIN opb_gpio
152 PARAMETER INSTANCE = LEDS
153 PARAMETER HW_VER = 3.01.b
154 PARAMETER C_GPIO_WIDTH = 4
155 PARAMETER C_IS_BIDIR = 0
156 PARAMETER C_BASEADDR = 0x40020000
157 PARAMETER C_HIGHADDR = 0x4002ffff
158 BUS_INTERFACE SOPB = mb_opb
159 PORT GPIO_d_out = GPIO_LED_out
160 END
161
162 BEGIN opb_emc
163 PARAMETER INSTANCE = FLASH
164 PARAMETER HW_VER = 2.00.a
165 PARAMETER C_NUM_BANKS_MEM = 1
166 PARAMETER C_MAX_MEM_WIDTH = 8
167 PARAMETER C_MEM0_WIDTH = 8
168 PARAMETER C_TCEDV_PS_MEM_0 = 70000
169 PARAMETER C_TAVDV_PS_MEM_0 = 70000
170 PARAMETER C_THZCE_PS_MEM_0 = 25000
171 PARAMETER C_TWC_PS_MEM_0 = 110000
172 PARAMETER C_TWP_PS_MEM_0 = 70000
173 PARAMETER C_TLZWE_PS_MEM_0 = 15000
174 PARAMETER C_OPB_CLK_PERIOD_PS = 20000
175 PARAMETER C_THZOE_PS_MEM_0 = 25000
176 PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
177 PARAMETER C_MEM0_BASEADDR = 0x20000000
178 PARAMETER C_MEM0_HIGHADDR = 0x2007FFFF
179 PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 0
180 BUS_INTERFACE SOPB = mb_opb
181 PORT Mem_A = FLASH_ADDR_split
182 PORT Mem_CEN = FLASH_CEN
183 PORT Mem_OEN = FLASH_OEN
184 PORT Mem_WEN = FLASH_WEN
185 PORT Mem_DQ = FLASH_DQ
186 END
187
188 BEGIN opb_gpio
189 PARAMETER INSTANCE = SEVENSEG
190 PARAMETER HW_VER = 3.01.b
191 PARAMETER C_GPIO_WIDTH = 13
192 PARAMETER C_BASEADDR = 0x40000000
193 PARAMETER C_HIGHADDR = 0x4000ffff
194 BUS_INTERFACE SOPB = mb_opb
195 PORT GPIO_d_out = GPIO_7SEG_OUT
196 END
197
198 BEGIN chipscope_icon
199 PARAMETER INSTANCE = chipscope_icon_0
200 PARAMETER HW_VER = 1.01.a
201 PORT control0 = ila_control0
202 END
203
204 BEGIN chipscope_ila
205 PARAMETER INSTANCE = chipscope_ila_0
206 PARAMETER HW_VER = 1.01.a
207 PARAMETER C_NUM_DATA_SAMPLES = 1024
208 PARAMETER C_TRIG0_TRIGGER_IN_WIDTH = 19
209 PARAMETER C_TRIG1_UNITS = 1
210 PARAMETER C_TRIG2_UNITS = 1
211 PORT CHIPSCOPE_ILA_CONTROL = ila_control0
212 PORT CLK = sys_clk_s
213 PORT TRIG0 = FLASH_ADDR
214 END
215
216 BEGIN util_bus_split
217 PARAMETER INSTANCE = flash_split
218 PARAMETER HW_VER = 1.00.a
219 PARAMETER C_SIZE_IN = 32
220 PARAMETER C_SPLIT = 13
221 PORT Sig = FLASH_ADDR_split
222 PORT Out2 = FLASH_ADDR
223 END
224
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