84f04dd95724c2b9c0280da536dbef1236ba1228
[raggedstone] / dhwk / source / top.vhd
1 -- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007
2
3
4
5 LIBRARY ieee;
6
7 USE ieee.std_logic_1164.ALL;
8 USE ieee.numeric_std.ALL;
9
10
11 entity dhwk is
12 Port ( KONST_1 : In std_logic;
13 PCI_CBEn : In std_logic_vector (3 downto 0);
14 PCI_CLOCK : In std_logic;
15 PCI_FRAMEn : In std_logic;
16 PCI_IDSEL : In std_logic;
17 PCI_IRDYn : In std_logic;
18 PCI_RSTn : In std_logic;
19 -- SERIAL_IN : In std_logic;
20 -- SPC_RDY_IN : In std_logic;
21 TAST_RESn : In std_logic;
22 TAST_SETn : In std_logic;
23 LED_2 : out std_logic;
24 LED_3 : out std_logic;
25 LED_4 : out std_logic;
26 LED_5 : out std_logic;
27 PCI_AD : InOut std_logic_vector (31 downto 0);
28 PCI_PAR : InOut std_logic;
29 PCI_DEVSELn : Out std_logic;
30 PCI_INTAn : Out std_logic;
31 PCI_PERRn : Out std_logic;
32 PCI_SERRn : Out std_logic;
33 PCI_STOPn : Out std_logic;
34 PCI_TRDYn : Out std_logic;
35 -- SERIAL_OUT : Out std_logic;
36 -- SPC_RDY_OUT : Out std_logic;
37 TB_IDSEL : Out std_logic;
38 TB_nDEVSEL : Out std_logic;
39 TB_nINTA : Out std_logic );
40 end dhwk;
41
42 architecture SCHEMATIC of dhwk is
43
44 SIGNAL gnd : std_logic := '0';
45 SIGNAL vcc : std_logic := '1';
46
47 signal READ_XX7_6 : std_logic;
48 signal RESERVE : std_logic;
49 signal SR_ERROR : std_logic;
50 signal R_ERROR : std_logic;
51 signal S_ERROR : std_logic;
52 signal WRITE_XX3_2 : std_logic;
53 signal WRITE_XX5_4 : std_logic;
54 signal WRITE_XX7_6 : std_logic;
55 signal READ_XX1_0 : std_logic;
56 signal READ_XX3_2 : std_logic;
57 signal INTAn : std_logic;
58 signal TRDYn : std_logic;
59 signal READ_XX5_4 : std_logic;
60 signal DEVSELn : std_logic;
61 signal FIFO_RDn : std_logic;
62 signal WRITE_XX1_0 : std_logic;
63 signal REG_OUT_XX6 : std_logic_vector (7 downto 0);
64 signal SYNC_FLAG : std_logic_vector (7 downto 0);
65 signal INT_REG : std_logic_vector (7 downto 0);
66 signal REVISON_ID : std_logic_vector (7 downto 0);
67 signal VENDOR_ID : std_logic_vector (15 downto 0);
68 signal READ_SEL : std_logic_vector (1 downto 0);
69 signal AD_REG : std_logic_vector (31 downto 0);
70 signal REG_OUT_XX7 : std_logic_vector (7 downto 0);
71 signal R_EFn : std_logic;
72 signal R_FFn : std_logic;
73 signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);
74 signal R_HFn : std_logic;
75 signal S_EFn : std_logic;
76 signal S_FFn : std_logic;
77 signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);
78 signal S_HFn : std_logic;
79 signal R_FIFO_D_IN : std_logic_vector (7 downto 0);
80 signal R_FIFO_READn : std_logic;
81 signal R_FIFO_RESETn : std_logic;
82 signal R_FIFO_RTn : std_logic;
83 signal R_FIFO_WRITEn : std_logic;
84 signal S_FIFO_D_IN : std_logic_vector (7 downto 0);
85 signal S_FIFO_READn : std_logic;
86 signal S_FIFO_RESETn : std_logic;
87 signal S_FIFO_RTn : std_logic;
88 signal S_FIFO_WRITEn : std_logic;
89 signal SERIAL_IN : std_logic;
90 signal SPC_RDY_IN : std_logic;
91 signal SERIAL_OUT : std_logic;
92 signal SPC_RDY_OUT : std_logic;
93 signal watch : std_logic;
94 signal control0 : std_logic_vector(35 downto 0);
95 signal data : std_logic_vector(95 downto 0);
96 signal trig0 : std_logic_vector(31 downto 0);
97
98 component MESS_1_TB
99 Port ( DEVSELn : In std_logic;
100 INTAn : In std_logic;
101 KONST_1 : In std_logic;
102 PCI_IDSEL : In std_logic;
103 REG_OUT_XX7 : In std_logic_vector (7 downto 0);
104 TB_DEVSELn : Out std_logic;
105 TB_INTAn : Out std_logic;
106 TB_PCI_IDSEL : Out std_logic );
107 end component;
108
109 component VEN_REV_ID
110 Port ( REV_ID : Out std_logic_vector (7 downto 0);
111 VEN_ID : Out std_logic_vector (15 downto 0) );
112 end component;
113
114 component INTERRUPT
115 Port ( INT_IN_0 : In std_logic;
116 INT_IN_1 : In std_logic;
117 INT_IN_2 : In std_logic;
118 INT_IN_3 : In std_logic;
119 INT_IN_4 : In std_logic;
120 INT_IN_5 : In std_logic;
121 INT_IN_6 : In std_logic;
122 INT_IN_7 : In std_logic;
123 INT_MASKE : In std_logic_vector (7 downto 0);
124 INT_RES : In std_logic_vector (7 downto 0);
125 PCI_CLOCK : In std_logic;
126 PCI_RSTn : In std_logic;
127 READ_XX5_4 : In std_logic;
128 RESET : In std_logic;
129 TAST_RESn : In std_logic;
130 TAST_SETn : In std_logic;
131 TRDYn : In std_logic;
132 INT_REG : Out std_logic_vector (7 downto 0);
133 INTAn : Out std_logic;
134 PCI_INTAn : Out std_logic );
135 end component;
136
137 component FIFO_CONTROL
138 Port ( FIFO_RDn : In std_logic;
139 FLAG_IN_0 : In std_logic;
140 FLAG_IN_4 : In std_logic;
141 HOLD : In std_logic;
142 KONST_1 : In std_logic;
143 PCI_CLOCK : In std_logic;
144 PSC_ENABLE : In std_logic;
145 R_EFn : In std_logic;
146 R_FFn : In std_logic;
147 R_HFn : In std_logic;
148 RESET : In std_logic;
149 S_EFn : In std_logic;
150 S_FFn : In std_logic;
151 S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);
152 S_HFn : In std_logic;
153 SERIAL_IN : In std_logic;
154 SPC_ENABLE : In std_logic;
155 SPC_RDY_IN : In std_logic;
156 WRITE_XX1_0 : In std_logic;
157 R_ERROR : Out std_logic;
158 R_FIFO_D_IN : Out std_logic_vector (7 downto 0);
159 R_FIFO_READn : Out std_logic;
160 R_FIFO_RESETn : Out std_logic;
161 R_FIFO_RETRANSMITn : Out std_logic;
162 R_FIFO_WRITEn : Out std_logic;
163 RESERVE : Out std_logic;
164 S_ERROR : Out std_logic;
165 S_FIFO_READn : Out std_logic;
166 S_FIFO_RESETn : Out std_logic;
167 S_FIFO_RETRANSMITn : Out std_logic;
168 S_FIFO_WRITEn : Out std_logic;
169 SERIAL_OUT : Out std_logic;
170 SPC_RDY_OUT : Out std_logic;
171 SR_ERROR : Out std_logic;
172 SYNC_FLAG : Out std_logic_vector (7 downto 0) );
173 end component;
174
175 component PCI_TOP
176 Port ( FLAG : In std_logic_vector (7 downto 0);
177 INT_REG : In std_logic_vector (7 downto 0);
178 PCI_CBEn : In std_logic_vector (3 downto 0);
179 PCI_CLOCK : In std_logic;
180 PCI_FRAMEn : In std_logic;
181 PCI_IDSEL : In std_logic;
182 PCI_IRDYn : In std_logic;
183 PCI_RSTn : In std_logic;
184 R_FIFO_Q : In std_logic_vector (7 downto 0);
185 REVISON_ID : In std_logic_vector (7 downto 0);
186 VENDOR_ID : In std_logic_vector (15 downto 0);
187 PCI_AD : InOut std_logic_vector (31 downto 0);
188 PCI_PAR : InOut std_logic;
189 AD_REG : Out std_logic_vector (31 downto 0);
190 DEVSELn : Out std_logic;
191 FIFO_RDn : Out std_logic;
192 PCI_DEVSELn : Out std_logic;
193 PCI_PERRn : Out std_logic;
194 PCI_SERRn : Out std_logic;
195 PCI_STOPn : Out std_logic;
196 PCI_TRDYn : Out std_logic;
197 READ_SEL : Out std_logic_vector (1 downto 0);
198 READ_XX1_0 : Out std_logic;
199 READ_XX3_2 : Out std_logic;
200 READ_XX5_4 : Out std_logic;
201 READ_XX7_6 : Out std_logic;
202 REG_OUT_XX0 : Out std_logic_vector (7 downto 0);
203 REG_OUT_XX6 : Out std_logic_vector (7 downto 0);
204 REG_OUT_XX7 : Out std_logic_vector (7 downto 0);
205 TRDYn : Out std_logic;
206 WRITE_XX1_0 : Out std_logic;
207 WRITE_XX3_2 : Out std_logic;
208 WRITE_XX5_4 : Out std_logic;
209 WRITE_XX7_6 : Out std_logic );
210 end component;
211
212 component fifo_generator_v3_2
213 port (
214 clk: IN std_logic;
215 din: IN std_logic_VECTOR(7 downto 0);
216 rd_en: IN std_logic;
217 rst: IN std_logic;
218 wr_en: IN std_logic;
219 almost_empty: OUT std_logic;
220 almost_full: OUT std_logic;
221 dout: OUT std_logic_VECTOR(7 downto 0);
222 empty: OUT std_logic;
223 full: OUT std_logic;
224 prog_full: OUT std_logic);
225 end component;
226
227 component icon
228 port
229 (
230 control0 : out std_logic_vector(35 downto 0)
231 );
232 end component;
233
234 component ila
235 port
236 (
237 control : in std_logic_vector(35 downto 0);
238 clk : in std_logic;
239 data : in std_logic_vector(95 downto 0);
240 trig0 : in std_logic_vector(31 downto 0)
241 );
242 end component;
243
244
245 begin
246 SERIAL_IN <= SERIAL_OUT;
247 SPC_RDY_IN <= SPC_RDY_OUT;
248 LED_2 <= TAST_RESn;
249 LED_3 <= TAST_SETn;
250 LED_4 <= '0';
251 LED_5 <= not watch;
252 PCI_INTAn <= watch;
253 trig0(31 downto 0) <= (
254 0 => watch,
255 1 => R_FIFO_READn,
256 2 => R_FIFO_WRITEn,
257 3 => S_FIFO_READn,
258 4 => S_FIFO_WRITEn,
259 16 => PCI_AD(0),
260 17 => PCI_AD(1),
261 18 => PCI_AD(2),
262 19 => PCI_AD(3),
263 20 => PCI_AD(4),
264 21 => PCI_AD(5),
265 22 => PCI_AD(6),
266 23 => PCI_AD(7),
267 27 => PCI_FRAMEn,
268 28 => PCI_CBEn(0),
269 29 => PCI_CBEn(1),
270 30 => PCI_CBEn(2),
271 31 => PCI_CBEn(3),
272 others => '0');
273
274 data(0) <= watch;
275 data(1) <= R_EFn;
276 data(2) <= R_HFn;
277 data(3) <= R_FFn;
278 data(4) <= R_FIFO_READn;
279 data(5) <= R_FIFO_RESETn;
280 data(6) <= R_FIFO_RTn;
281 data(7) <= R_FIFO_WRITEn;
282 data(8) <= S_EFn;
283 data(9) <= S_HFn;
284 data(10) <= S_FFn;
285 data(11) <= S_FIFO_READn;
286 data(12) <= S_FIFO_RESETn;
287 data(13) <= S_FIFO_RTn;
288 data(14) <= S_FIFO_WRITEn;
289 data(15) <= SERIAL_IN;
290 data(16) <= SPC_RDY_IN;
291 data(17) <= SERIAL_OUT;
292 data(18) <= SPC_RDY_OUT;
293 data(26 downto 19) <= S_FIFO_Q_OUT;
294 data(34 downto 27) <= R_FIFO_Q_OUT;
295 data(66 downto 35) <= PCI_AD(31 downto 0);
296 data(70 downto 67) <= PCI_CBEn(3 downto 0);
297 data(71) <= PCI_FRAMEn;
298
299 I19 : MESS_1_TB
300 Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,
301 PCI_IDSEL=>PCI_IDSEL,
302 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
303 TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,
304 TB_PCI_IDSEL=>TB_IDSEL );
305 I18 : VEN_REV_ID
306 Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),
307 VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );
308 I16 : INTERRUPT
309 Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),
310 INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,
311 INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,
312 INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),
313 INT_RES(7 downto 0)=>AD_REG(7 downto 0),
314 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,
315 READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),
316 TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,
317 TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),
318 INTAn=>INTAn, PCI_INTAn=>watch);
319 I14 : FIFO_CONTROL
320 Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,
321 FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,
322 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),
323 R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,
324 RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,
325 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),
326 S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,
327 SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,
328 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,
329 R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),
330 R_FIFO_READn=>R_FIFO_READn,
331 R_FIFO_RESETn=>R_FIFO_RESETn,
332 R_FIFO_RETRANSMITn=>R_FIFO_RTn,
333 R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,
334 S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,
335 S_FIFO_RESETn=>S_FIFO_RESETn,
336 S_FIFO_RETRANSMITn=>S_FIFO_RTn,
337 S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,
338 SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,
339 SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );
340 I1 : PCI_TOP
341 Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),
342 INT_REG(7 downto 0)=>INT_REG(7 downto 0),
343 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),
344 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,
345 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,
346 PCI_RSTn=>PCI_RSTn,
347 R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),
348 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),
349 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),
350 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),
351 PCI_PAR=>PCI_PAR,
352 AD_REG(31 downto 0)=>AD_REG(31 downto 0),
353 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,
354 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,
355 PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,
356 PCI_TRDYn=>PCI_TRDYn,
357 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),
358 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,
359 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,
360 REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),
361 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),
362 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),
363 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,
364 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,
365 WRITE_XX7_6=>WRITE_XX7_6 );
366
367 receive_fifo : fifo_generator_v3_2
368 port map (
369 clk => PCI_CLOCK,
370 din => R_FIFO_D_IN,
371 rd_en => not R_FIFO_READn,
372 rst => not R_FIFO_RESETn,
373 wr_en => not R_FIFO_WRITEn,
374 dout => R_FIFO_Q_OUT,
375 empty => R_EFn,
376 full => R_FFn,
377 prog_full => R_HFn);
378
379 send_fifo : fifo_generator_v3_2
380 port map (
381 clk => PCI_CLOCK,
382 din => S_FIFO_D_IN,
383 rd_en => not S_FIFO_READn,
384 rst => not S_FIFO_RESETn,
385 wr_en => not S_FIFO_WRITEn,
386 dout => S_FIFO_Q_OUT,
387 empty => S_EFn,
388 full => S_FFn,
389 prog_full => S_HFn);
390
391 i_icon : icon
392 port map
393 (
394 control0 => control0
395 );
396
397 i_ila : ila
398 port map
399 (
400 control => control0,
401 clk => PCI_CLOCK,
402 data => data,
403 trig0 => trig0
404 );
405 end SCHEMATIC;
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