8b50c2e7543159cf4bf8440f6743579475813fdf
[raggedstone] / dhwk / source / Io_reg.vhd
1 -- J.STELZNER
2 -- INFORMATIK-3 LABOR
3 -- 23.08.2006
4 -- File: IO_MUX.VHD
5
6 library ieee;
7 use ieee.std_logic_1164.all;
8
9 entity IO_REG is
10 port
11 (
12 PCI_CLOCK :in std_logic;
13 PCI_RSTn :in std_logic;
14 PCI_FRAMEn :in std_logic;
15 PCI_IRDYn :in std_logic;
16 PCI_IDSEL :in std_logic;
17 PCI_PAR :in std_logic;
18 PCI_CBEn :in std_logic_vector ( 3 downto 0);
19 OE_PCI_AD :in std_logic;
20 IO_DATA :in std_logic_vector (31 downto 0);
21 AD_REG :out std_logic_vector (31 downto 0);
22 CBE_REGn :out std_logic_vector ( 3 downto 0);
23 FRAME_REGn :out std_logic;
24 IRDY_REGn :out std_logic;
25 IDSEL_REG :out std_logic;
26 PAR_REG :out std_logic;
27 PCI_AD :out std_logic_vector (31 downto 0) -- t/s
28 );
29 end entity IO_REG;
30
31 architecture IO_REG_DESIGN of IO_REG is
32
33 signal REG_AD :std_logic_vector (31 downto 0);
34 signal REG_CBEn :std_logic_vector ( 3 downto 0);
35 signal REG_FRAMEn :std_logic;
36 signal REG_IRDYn :std_logic;
37 signal REG_IDSEL :std_logic;
38 signal REG_PAR :std_logic;
39
40 begin
41
42 process (PCI_CLOCK, PCI_RSTn)
43 begin
44 if PCI_RSTn = '0' then
45
46 REG_AD <= X"00000000";
47 REG_CBEn <= "0000";
48 REG_FRAMEn <= '1';
49 REG_IRDYn <= '1';
50 REG_IDSEL <= '0';
51 REG_PAR <= '0';
52
53 elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
54
55 REG_AD <= IO_DATA;
56 REG_CBEn <= PCI_CBEn;
57 REG_FRAMEn <= PCI_FRAMEn;
58 REG_IRDYn <= PCI_IRDYn;
59 REG_IDSEL <= PCI_IDSEL;
60 REG_PAR <= PCI_PAR;
61
62 end if;
63 end process;
64
65 PCI_AD <= REG_AD when OE_PCI_AD ='1' else (others => 'Z');
66
67 AD_REG <= REG_AD;
68 CBE_REGn <= REG_CBEn;
69 FRAME_REGn <= REG_FRAMEn;
70 IRDY_REGn <= REG_IRDYn;
71 IDSEL_REG <= REG_IDSEL;
72 PAR_REG <= REG_PAR;
73
74 end architecture IO_REG_DESIGN;
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