8c906901ecb8b677cb339ffc0c60caf7a99d8004
[raggedstone] / ethernet / source / top.vhd
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 entity ethernet is
5 PORT(
6 PCI_AD : INOUT std_logic_vector(31 downto 0);
7 PCI_CLOCK : IN std_logic;
8 PCI_IDSEL : IN std_logic;
9 PCI_CBEn : INOUT std_logic_vector (3 downto 0);
10 PCI_FRAMEn : INOUT std_logic;
11 PCI_IRDYn : INOUT std_logic;
12 PCI_RSTn : INOUT std_logic;
13 PCI_DEVSELn : INOUT std_logic;
14 PCI_INTAn : INOUT std_logic;
15 PCI_PERRn : INOUT std_logic;
16 PCI_SERRn : INOUT std_logic;
17 PCI_STOPn : INOUT std_logic;
18 PCI_TRDYn : INOUT std_logic;
19 PCI_PAR : INOUT std_logic;
20 PCI_REQn : OUT std_logic;
21 PCI_GNTn : IN std_logic;
22
23 MTX_CLK_PAD_I : IN std_logic;
24 MTXD_PAD_O : OUT std_logic_vector (3 downto 0);
25 MTXEN_PAD_O : OUT std_logic;
26 MRX_CLK_PAD_I : IN std_logic;
27 MRXD_PAD_I : IN std_logic_vector (3 downto 0);
28 MRXDV_PAD_I : IN std_logic;
29 MRXERR_PAD_I : IN std_logic;
30 MCOLL_PAD_I : IN std_logic;
31 MCRS_PAD_I : IN std_logic;
32 MD_PAD_IO : INOUT std_logic;
33 MDC_PAD_O : OUT std_logic;
34
35 LED_2 : OUT std_logic
36 );
37 end ethernet;
38
39 architecture ethernet_arch of ethernet is
40
41 COMPONENT eth_top
42 PORT(
43 wb_clk_i : IN std_logic;
44 wb_rst_i : IN std_logic;
45 wb_dat_i : IN std_logic_vector(31 downto 0);
46 wb_adr_i : IN std_logic_vector(11 downto 2);
47 wb_sel_i : IN std_logic_vector(3 downto 0);
48 wb_we_i : IN std_logic;
49 wb_cyc_i : IN std_logic;
50 wb_stb_i : IN std_logic;
51 m_wb_dat_i : IN std_logic_vector(31 downto 0);
52 m_wb_ack_i : IN std_logic;
53 m_wb_err_i : IN std_logic;
54 mtx_clk_pad_i : IN std_logic;
55 mrx_clk_pad_i : IN std_logic;
56 mrxd_pad_i : IN std_logic_vector(3 downto 0);
57 mrxdv_pad_i : IN std_logic;
58 mrxerr_pad_i : IN std_logic;
59 mcoll_pad_i : IN std_logic;
60 mcrs_pad_i : IN std_logic;
61 md_pad_i : IN std_logic;
62 wb_dat_o : OUT std_logic_vector(31 downto 0);
63 wb_ack_o : OUT std_logic;
64 wb_err_o : OUT std_logic;
65 m_wb_adr_o : OUT std_logic_vector(31 downto 0);
66 m_wb_sel_o : OUT std_logic_vector(3 downto 0);
67 m_wb_we_o : OUT std_logic;
68 m_wb_dat_o : OUT std_logic_vector(31 downto 0);
69 m_wb_cyc_o : OUT std_logic;
70 m_wb_stb_o : OUT std_logic;
71 mtxd_pad_o : OUT std_logic_vector(3 downto 0);
72 mtxen_pad_o : OUT std_logic;
73 mtxerr_pad_o : OUT std_logic;
74 mdc_pad_o : OUT std_logic;
75 md_pad_o : OUT std_logic;
76 md_padoe_o : OUT std_logic;
77 m_wb_cti_o : OUT std_logic_vector(2 downto 0);
78 m_wb_bte_o : OUT std_logic_vector(1 downto 0);
79 int_o : OUT std_logic
80 );
81 END COMPONENT;
82
83 COMPONENT pci_bridge32
84 PORT(
85 wb_clk_i : IN std_logic;
86 wb_rst_i : IN std_logic;
87 wb_int_i : IN std_logic;
88 wbs_adr_i : IN std_logic_vector(31 downto 0);
89 wbs_dat_i : IN std_logic_vector(31 downto 0);
90 wbs_sel_i : IN std_logic_vector(3 downto 0);
91 wbs_cyc_i : IN std_logic;
92 wbs_stb_i : IN std_logic;
93 wbs_we_i : IN std_logic;
94 wbs_cti_i : IN std_logic_vector(2 downto 0);
95 wbs_bte_i : IN std_logic_vector(1 downto 0);
96 wbm_dat_i : IN std_logic_vector(31 downto 0);
97 wbm_ack_i : IN std_logic;
98 wbm_rty_i : IN std_logic;
99 wbm_err_i : IN std_logic;
100 pci_clk_i : IN std_logic;
101 pci_rst_i : IN std_logic;
102 pci_inta_i : IN std_logic;
103 pci_gnt_i : IN std_logic;
104 pci_frame_i : IN std_logic;
105 pci_irdy_i : IN std_logic;
106 pci_idsel_i : IN std_logic;
107 pci_devsel_i : IN std_logic;
108 pci_trdy_i : IN std_logic;
109 pci_stop_i : IN std_logic;
110 pci_ad_i : IN std_logic_vector(31 downto 0);
111 pci_cbe_i : IN std_logic_vector(3 downto 0);
112 pci_par_i : IN std_logic;
113 pci_perr_i : IN std_logic;
114 wb_rst_o : OUT std_logic;
115 wb_int_o : OUT std_logic;
116 wbs_dat_o : OUT std_logic_vector(31 downto 0);
117 wbs_ack_o : OUT std_logic;
118 wbs_rty_o : OUT std_logic;
119 wbs_err_o : OUT std_logic;
120 wbm_adr_o : OUT std_logic_vector(31 downto 0);
121 wbm_dat_o : OUT std_logic_vector(31 downto 0);
122 wbm_sel_o : OUT std_logic_vector(3 downto 0);
123 wbm_cyc_o : OUT std_logic;
124 wbm_stb_o : OUT std_logic;
125 wbm_we_o : OUT std_logic;
126 wbm_cti_o : OUT std_logic_vector(2 downto 0);
127 wbm_bte_o : OUT std_logic_vector(1 downto 0);
128 pci_rst_o : OUT std_logic;
129 pci_inta_o : OUT std_logic;
130 pci_rst_oe_o : OUT std_logic;
131 pci_inta_oe_o : OUT std_logic;
132 pci_req_o : OUT std_logic;
133 pci_req_oe_o : OUT std_logic;
134 pci_frame_o : OUT std_logic;
135 pci_frame_oe_o : OUT std_logic;
136 pci_irdy_oe_o : OUT std_logic;
137 pci_devsel_oe_o : OUT std_logic;
138 pci_trdy_oe_o : OUT std_logic;
139 pci_stop_oe_o : OUT std_logic;
140 pci_ad_oe_o : OUT std_logic_vector(31 downto 0);
141 pci_cbe_oe_o : OUT std_logic_vector(3 downto 0);
142 pci_irdy_o : OUT std_logic;
143 pci_devsel_o : OUT std_logic;
144 pci_trdy_o : OUT std_logic;
145 pci_stop_o : OUT std_logic;
146 pci_ad_o : OUT std_logic_vector(31 downto 0);
147 pci_cbe_o : OUT std_logic_vector(3 downto 0);
148 pci_par_o : OUT std_logic;
149 pci_par_oe_o : OUT std_logic;
150 pci_perr_o : OUT std_logic;
151 pci_perr_oe_o : OUT std_logic;
152 pci_serr_o : OUT std_logic;
153 pci_serr_oe_o : OUT std_logic
154 );
155 END COMPONENT;
156
157 signal pci_rst_o : std_logic;
158 signal pci_rst_oe_o : std_logic;
159 signal pci_inta_o : std_logic;
160 signal pci_inta_oe_o : std_logic;
161 signal pci_req_o : std_logic;
162 signal pci_req_oe_o : std_logic;
163 signal pci_frame_o : std_logic;
164 signal pci_frame_oe_o : std_logic;
165 signal pci_irdy_o : std_logic;
166 signal pci_irdy_oe_o : std_logic;
167 signal pci_devsel_o : std_logic;
168 signal pci_devsel_oe_o : std_logic;
169 signal pci_trdy_o : std_logic;
170 signal pci_trdy_oe_o : std_logic;
171 signal pci_stop_o : std_logic;
172 signal pci_stop_oe_o : std_logic;
173 signal pci_par_o : std_logic;
174 signal pci_par_oe_o : std_logic;
175 signal pci_perr_o : std_logic;
176 signal pci_perr_oe_o : std_logic;
177 signal pci_serr_o : std_logic;
178 signal pci_serr_oe_o : std_logic;
179 signal pci_ad_oe_o : std_logic_vector(31 downto 0);
180 signal pci_cbe_oe_o : std_logic_vector(3 downto 0);
181 signal pci_ad_o : std_logic_vector (31 downto 0);
182 signal pci_cbe_o : std_logic_vector (3 downto 0);
183
184 signal wb_clk_i : std_logic;
185 signal wb_rst_i : std_logic;
186 signal wb_dat_i : std_logic_vector (31 downto 0);
187 signal wb_dat_o : std_logic_vector (31 downto 0);
188 signal wb_adr_i : std_logic_vector (11 downto 2);
189 signal wb_sel_i : std_logic_vector (3 downto 0);
190 signal wb_we_i : std_logic;
191 signal wb_cyc_i : std_logic;
192 signal wb_stb_i : std_logic;
193 signal wb_ack_o : std_logic;
194 signal wb_err_o : std_logic;
195 signal m_wb_adr_o : std_logic_vector(31 downto 0);
196 signal m_wb_sel_o : std_logic_vector(3 downto 0);
197 signal m_wb_we_o : std_logic;
198 signal m_wb_dat_o : std_logic_vector(31 downto 0);
199 signal m_wb_dat_i : std_logic_vector(31 downto 0);
200 signal m_wb_cyc_o : std_logic;
201 signal m_wb_stb_o : std_logic;
202 signal m_wb_ack_i : std_logic;
203 signal m_wb_err_i : std_logic;
204 signal md_pad_o : std_logic;
205 signal md_padoe_o : std_logic;
206 signal int_o : std_logic;
207 signal wbm_adr_o : std_logic_vector(31 downto 0);
208
209 signal m_wb_cti_o : std_logic_vector(2 downto 0);
210 signal m_wb_bte_o : std_logic_vector(1 downto 0);
211
212 BEGIN
213
214 PCI_RSTn <= pci_rst_o when (pci_rst_oe_o = '1') else 'Z';
215 PCI_INTAn <= pci_inta_o when (pci_inta_oe_o = '1') else 'Z';
216 PCI_REQn <= pci_req_o when (pci_req_oe_o = '1') else 'Z';
217 PCI_FRAMEn <= pci_frame_o when (pci_frame_oe_o = '1') else 'Z';
218 PCI_IRDYn <= pci_irdy_o when (pci_irdy_oe_o = '1') else 'Z';
219 PCI_DEVSELn <= pci_devsel_o when (pci_devsel_oe_o = '1') else 'Z';
220 PCI_TRDYn <= pci_trdy_o when (pci_trdy_oe_o = '1') else 'Z';
221 PCI_STOPn <= pci_stop_o when (pci_stop_oe_o = '1') else 'Z';
222 PCI_PAR <= pci_par_o when (pci_par_oe_o = '1') else 'Z';
223 PCI_PERRn <= pci_perr_o when (pci_perr_oe_o = '1') else 'Z';
224 PCI_SERRn <= pci_serr_o when (pci_serr_oe_o = '1') else 'Z';
225 MD_PAD_IO <= md_pad_o when (md_padoe_o = '1') else 'Z';
226
227 BLA1: FOR i in 31 downto 0 generate
228 PCI_AD(i) <= pci_ad_o(i) when (pci_ad_oe_o(i) = '1') else 'Z';
229 end generate;
230
231 BLA2: FOR i in 3 downto 0 generate
232 PCI_CBEn(i) <= pci_cbe_o(i) when (pci_cbe_oe_o(i) = '1') else 'Z';
233 end generate;
234
235 wb_adr_i <= wbm_adr_o (11 downto 2);
236
237 Inst_pci_bridge32: pci_bridge32 PORT MAP(
238 wb_clk_i => wb_clk_i ,
239 wb_rst_i => '0',
240 wb_rst_o => wb_rst_i,
241 wb_int_i => int_o,
242 -- wb_int_o => ,
243 wbs_adr_i => m_wb_adr_o ,
244 wbs_dat_i => m_wb_dat_o,
245 wbs_dat_o => m_wb_dat_i,
246 wbs_sel_i => m_wb_sel_o,
247 wbs_cyc_i => m_wb_cyc_o,
248 wbs_stb_i => m_wb_stb_o,
249 wbs_we_i => m_wb_we_o,
250 wbs_cti_i => m_wb_cti_o,
251 wbs_bte_i => m_wb_bte_o,
252 wbs_ack_o => m_wb_ack_i,
253 -- wbs_rty_o => ,
254 wbs_err_o => m_wb_err_i,
255 wbm_adr_o => wbm_adr_o,
256 wbm_dat_i => wb_dat_o,
257 wbm_dat_o => wb_dat_i,
258 wbm_sel_o => wb_sel_i,
259 wbm_cyc_o => wb_cyc_i,
260 wbm_stb_o => wb_stb_i,
261 wbm_we_o => wb_we_i,
262 -- wbm_cti_o => ,
263 -- wbm_bte_o => ,
264 wbm_ack_i => wb_ack_o ,
265 wbm_rty_i => '0',
266 wbm_err_i => wb_err_o,
267 pci_clk_i => PCI_CLOCK,
268 pci_rst_i => PCI_RSTn,
269 pci_rst_o => pci_rst_o ,
270 pci_rst_oe_o => pci_rst_oe_o,
271 pci_inta_i => PCI_INTAn,
272 pci_inta_o => pci_inta_o,
273 pci_inta_oe_o => pci_inta_oe_o,
274 pci_req_o => pci_req_o,
275 pci_req_oe_o => pci_req_oe_o,
276 pci_gnt_i => PCI_GNTn,
277 pci_frame_i => PCI_FRAMEn,
278 pci_frame_o => pci_frame_o,
279 pci_frame_oe_o => pci_frame_oe_o,
280 pci_irdy_oe_o => pci_irdy_oe_o,
281 pci_devsel_oe_o => pci_devsel_oe_o,
282 pci_trdy_oe_o => pci_trdy_oe_o,
283 pci_stop_oe_o => pci_stop_oe_o,
284 pci_ad_oe_o => pci_ad_oe_o,
285 pci_cbe_oe_o => pci_cbe_oe_o,
286 pci_irdy_i => PCI_IRDYn,
287 pci_irdy_o => pci_irdy_o,
288 pci_idsel_i => PCI_IDSEL,
289 pci_devsel_i => PCI_DEVSELn,
290 pci_devsel_o => pci_devsel_o,
291 pci_trdy_i => PCI_TRDYn,
292 pci_trdy_o => pci_trdy_o,
293 pci_stop_i => PCI_STOPn,
294 pci_stop_o => pci_stop_o,
295 pci_ad_i => PCI_AD,
296 pci_ad_o => pci_ad_o,
297 pci_cbe_i => PCI_CBEn,
298 pci_cbe_o => pci_cbe_o,
299 pci_par_i => PCI_PAR,
300 pci_par_o => pci_par_o,
301 pci_par_oe_o => pci_par_oe_o,
302 pci_perr_i => PCI_PERRn,
303 pci_perr_o => pci_perr_o,
304 pci_perr_oe_o => pci_perr_oe_o,
305 pci_serr_o => pci_serr_o,
306 pci_serr_oe_o => pci_serr_oe_o
307 );
308
309 Inst_eth_top: eth_top PORT MAP(
310 wb_clk_i => wb_clk_i ,
311 wb_rst_i => wb_rst_i ,
312 wb_dat_i => wb_dat_i ,
313 wb_dat_o => wb_dat_o ,
314 wb_adr_i => wb_adr_i ,
315 wb_sel_i => wb_sel_i ,
316 wb_we_i => wb_we_i ,
317 wb_cyc_i => wb_cyc_i ,
318 wb_stb_i => wb_stb_i ,
319 wb_ack_o => wb_ack_o ,
320 wb_err_o => wb_err_o ,
321 m_wb_adr_o => m_wb_adr_o,
322 m_wb_sel_o => m_wb_sel_o,
323 m_wb_we_o => m_wb_we_o ,
324 m_wb_dat_o => m_wb_dat_o,
325 m_wb_dat_i => m_wb_dat_i,
326 m_wb_cyc_o => m_wb_cyc_o,
327 m_wb_stb_o => m_wb_stb_o,
328 m_wb_ack_i => m_wb_ack_i,
329 m_wb_err_i => m_wb_err_i,
330 mtx_clk_pad_i => MTX_CLK_PAD_I,
331 mtxd_pad_o => MTXD_PAD_O,
332 mtxen_pad_o => MTXEN_PAD_O,
333 mtxerr_pad_o => LED_2,
334 mrx_clk_pad_i => MRX_CLK_PAD_I,
335 mrxd_pad_i => MRXD_PAD_I,
336 mrxdv_pad_i => MRXDV_PAD_I,
337 mrxerr_pad_i => MRXERR_PAD_I,
338 mcoll_pad_i => MCOLL_PAD_I,
339 mcrs_pad_i => MCRS_PAD_I,
340 mdc_pad_o => MDC_PAD_O,
341 md_pad_i => MD_PAD_IO,
342 md_pad_o => md_pad_o,
343 md_padoe_o => md_padoe_o,
344 m_wb_cti_o => m_wb_cti_o,
345 m_wb_bte_o => m_wb_bte_o,
346 int_o => int_o
347 );
348
349 end architecture ethernet_arch;
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