906a9ca21f65244d6d8488cfe3e0256b82578c71
[raggedstone] / dhwk / source / config_04h.vhd
1 -- J.STELZNER
2 -- INFORMATIK-3 LABOR
3 -- 23.08.2006
4 -- File: CONFIG_04H.VHD
5
6 library IEEE;
7 use IEEE.std_logic_1164.all;
8
9 entity CONFIG_04H is
10 port
11 (
12 PCI_CLOCK :in std_logic;
13 PCI_RSTn :in std_logic;
14 SERR :in std_logic;
15 PERR :in std_logic;
16 AD_REG :in std_logic_vector(31 downto 0);
17 CBE_REGn :in std_logic_vector( 3 downto 0);
18 CONF_WR_04H :in std_logic;
19 CONF_DATA_04H :out std_logic_vector(31 downto 0)
20 );
21 end entity CONFIG_04H;
22
23 architecture CONFIG_04H_DESIGN of CONFIG_04H is
24
25 signal CONF_STATUS :std_logic_vector(31 downto 16);
26 signal CONF_COMMAND :std_logic_vector(15 downto 0);
27
28
29 begin
30
31 --*******************************************************************
32 --************* PCI Configuration Space Header "STATUS" *************
33 --*******************************************************************
34
35 CONF_STATUS(20 downto 16) <= "00000" ;-- Reserved
36 CONF_STATUS(21 ) <= '0' ;-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz
37 CONF_STATUS(22 ) <= '0' ;-- MAS/TAR: "R_O"
38 CONF_STATUS(23 ) <= '0' ;-- ???/???: "R_O" : fast back-to-back
39 CONF_STATUS(24 ) <= '0' ;-- Master :
40 --CONF_STATUS(26 downto 25) <= "00" ;-- Mas/Tar: "R_O" : timing fast for "DEVSEL"
41 CONF_STATUS(26 downto 25) <= "01" ;-- Mas/Tar: "R_O" : timing medium for "DEVSEL"
42 --CONF_STATUS(26 downto 25) <= "10" ;-- Mas/Tar: "R_O" : timing slow for "DEVSEL"
43 --CONF_STATUS(26 downto 25) <= "11" ;-- Mas/Tar: "R_O" : reserved
44 CONF_STATUS(27 ) <= '0' ;-- Target : "R_W" : Taget-Abort
45 CONF_STATUS(28 ) <= '0' ;-- Master : "R_W" : Taget-Abort
46 CONF_STATUS(29 ) <= '0' ;-- Master : "R_W" : Master-Abort
47 --CONF_STATUS(30 ) <= SERR ;-- Mas/Tar: "R_W" : SERR
48 --CONF_STATUS(31 ) <= PERR ;-- Mas/Tar: "R_W" : PERR
49
50 process (PCI_CLOCK,PCI_RSTn)
51 begin
52 if PCI_RSTn = '0' then CONF_STATUS(30) <= '0';
53 CONF_STATUS(31) <= '0';
54
55 elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
56
57 if CONF_WR_04H = '1' and CBE_REGn(3) = '0' then
58
59 CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30));
60 CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31));
61
62 else CONF_STATUS(30) <= SERR or CONF_STATUS(30);
63 CONF_STATUS(31) <= PERR or CONF_STATUS(31);
64
65 end if;
66 end if;
67 end process;
68
69 --*******************************************************************
70 --*********** PCI Configuration Space Header "COMMAND" **************
71 --*******************************************************************
72
73 -- CONF_COMMAND( 0) <= '0';-- I/O Space accesses ???
74 -- CONF_COMMAND( 1) <= '0';-- Mem Space accesses ???
75 -- CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus
76 -- CONF_COMMAND( 3) <= '0';-- Special Cycle ???
77 -- CONF_COMMAND( 4) <= '0';-- Master ???
78 -- CONF_COMMAND( 5) <= '0';-- VGA ???
79 -- CONF_COMMAND( 6) <= '0';-- Party checking enable/disable
80 CONF_COMMAND( 7) <= '0';-- address/data stepping ???
81 -- CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn"
82 -- CONF_COMMAND( 9) <= '0';-- fast back-to-back
83 -- CONF_COMMAND(10) <= '0';-- Reserved
84 -- CONF_COMMAND(11) <= '0';-- Reserved
85 -- CONF_COMMAND(12) <= '0';-- Reserved
86 -- CONF_COMMAND(13) <= '0';-- Reserved
87 -- CONF_COMMAND(14) <= '0';-- Reserved
88 -- CONF_COMMAND(15) <= '0';-- Reserved
89
90 process (PCI_CLOCK,PCI_RSTn)
91 begin
92 if PCI_RSTn = '0' then CONF_COMMAND(15 downto 8) <= (others =>'0');
93 CONF_COMMAND( 6 downto 0) <= (others =>'0');
94
95 elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
96
97 if CONF_WR_04H = '1'and CBE_REGn(1) = '0' then
98
99 CONF_COMMAND(15 downto 8) <= AD_REG(15 downto 8);
100 else CONF_COMMAND(15 downto 8) <= CONF_COMMAND(15 downto 8);
101 end if;
102
103
104 if CONF_WR_04H = '1'and CBE_REGn(0) = '0' then
105
106 CONF_COMMAND( 6 downto 0) <= AD_REG( 6 downto 0);
107 else CONF_COMMAND( 6 downto 0) <= CONF_COMMAND( 6 downto 0);
108 end if;
109
110 end if;
111 end process;
112
113 CONF_DATA_04H <= CONF_STATUS & CONF_COMMAND;
114
115 end architecture CONFIG_04H_DESIGN;
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