powercore
[raggedstone] / heartbeat / source / pfs.vhd
1 --+-----------------------------------------+
2 --| pfs |
3 --+-----------------------------------------+
4
5 library ieee;
6 use ieee.std_logic_1164.all;
7
8 entity pfs is
9 port (
10 clk : in std_logic;
11 a : in std_logic;
12 y : out std_logic
13
14 );
15 end pfs;
16
17 architecture rtl of pfs is
18
19 signal a_s : std_logic;
20
21 begin
22
23 SYNCP: process( clk, a )
24 begin
25
26 if ( rising_edge(clk) ) then
27 a_s <= a;
28 end if;
29
30 end process SYNCP;
31
32 y <= a and (not a_s);
33
34 end rtl;
35
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