98add0f6afdc431be6468692799b8b467d1c03c9
[raggedstone] / dhwk_old / source / top_dhwk.vhd
1 --+-------------------------------------------------------------------------------------------------+
2 --| |
3 --| File: top.vhd |
4 --| |
5 --| Components: pci32lite.vhd |
6 --| pciwbsequ.vhd |
7 --| pcidmux.vhd |
8 --| pciregs.vhd |
9 --| pcipargen.vhd |
10 --| -- Libs -- |
11 --| ona.vhd |
12 --| |
13 --| Description: RS1 PCI Demo : (TOP) Main file. |
14 --| |
15 --| |
16 --| |
17 --+-------------------------------------------------------------------------------------------------+
18 --| |
19 --| Revision history : |
20 --| Date Version Author Description |
21 --| |
22 --| |
23 --| To do: |
24 --| |
25 --+-------------------------------------------------------------------------------------------------+
26
27
28 --+-----------------------------------------------------------------------------+
29 --| LIBRARIES |
30 --+-----------------------------------------------------------------------------+
31
32 library ieee;
33 use ieee.std_logic_1164.all;
34 use ieee.std_logic_arith.all;
35 use ieee.std_logic_unsigned.all;
36
37 --+-----------------------------------------------------------------------------+
38 --| ENTITY |
39 --+-----------------------------------------------------------------------------+
40
41 entity dhwk is
42 port (
43
44 -- General
45 PCI_CLK : in std_logic;
46 PCI_nRES : in std_logic;
47
48 -- PCI target 32bits
49 PCI_AD : inout std_logic_vector(31 downto 0);
50 PCI_CBE : in std_logic_vector(3 downto 0);
51 PCI_PAR : out std_logic;
52 PCI_nFRAME : in std_logic;
53 PCI_nIRDY : in std_logic;
54 PCI_nTRDY : out std_logic;
55 PCI_nDEVSEL : out std_logic;
56 PCI_nSTOP : out std_logic;
57 PCI_IDSEL : in std_logic;
58 PCI_nPERR : out std_logic;
59 PCI_nSERR : out std_logic;
60 PCI_nINT : out std_logic;
61
62 -- debug signals
63 LED3 : out std_logic;
64 LED2 : out std_logic;
65 LED4 : out std_logic;
66 LED5 : out std_logic
67
68 );
69 end dhwk;
70
71
72 --+-----------------------------------------------------------------------------+
73 --| ARCHITECTURE |
74 --+-----------------------------------------------------------------------------+
75
76 architecture dhwk_arch of dhwk is
77
78
79 --+-----------------------------------------------------------------------------+
80 --| COMPONENTS |
81 --+-----------------------------------------------------------------------------+
82
83 component pci32tlite
84 port (
85
86 -- General
87 clk33 : in std_logic;
88 nrst : in std_logic;
89
90 -- PCI target 32bits
91 ad : inout std_logic_vector(31 downto 0);
92 cbe : in std_logic_vector(3 downto 0);
93 par : out std_logic;
94 frame : in std_logic;
95 irdy : in std_logic;
96 trdy : out std_logic;
97 devsel : out std_logic;
98 stop : out std_logic;
99 idsel : in std_logic;
100 perr : out std_logic;
101 serr : out std_logic;
102 intb : out std_logic;
103
104 -- Master whisbone
105 wb_adr_o : out std_logic_vector(24 downto 1);
106 wb_dat_i : in std_logic_vector(15 downto 0);
107 wb_dat_o : out std_logic_vector(15 downto 0);
108 wb_sel_o : out std_logic_vector(1 downto 0);
109 wb_we_o : out std_logic;
110 wb_stb_o : out std_logic;
111 wb_cyc_o : out std_logic;
112 wb_ack_i : in std_logic;
113 wb_err_i : in std_logic;
114 wb_int_i : in std_logic;
115
116 -- debug signals
117 debug_init : out std_logic;
118 debug_access : out std_logic
119
120 );
121 end component;
122
123 component heartbeat
124 port (
125 clk_i : in std_logic;
126 nrst_i : in std_logic;
127 led2_o : out std_logic;
128 led3_o : out std_logic;
129 led4_o : out std_logic;
130 led5_o : out std_logic
131 );
132 end component;
133
134 component generic_fifo_sc_a
135 port (
136 clk : in std_logic;
137 rst : in std_logic;
138 clr : in std_logic;
139 din : in std_logic_vector(7 downto 0);
140 we : in std_logic;
141 dout : out std_logic_vector(7 downto 0);
142 re : in std_logic;
143 full : out std_logic;
144 full_r : out std_logic;
145 empty : out std_logic;
146 empty_r : out std_logic;
147 full_n : out std_logic;
148 full_n_r : out std_logic;
149 empty_n : out std_logic;
150 empty_n_r : out std_logic;
151 level : out std_logic_vector(1 downto 0)
152 );
153 end component;
154
155 component generic_dpram
156 port (
157 rclk : in std_logic;
158 rrst : in std_logic;
159 rce : in std_logic;
160 oe : in std_logic;
161 raddr : in std_logic_vector(11 downto 0);
162 do : out std_logic_vector(7 downto 0);
163 wclk : in std_logic;
164 wrst : in std_logic;
165 wce : in std_logic;
166 we : in std_logic;
167 waddr : in std_logic_vector(11 downto 0);
168 di : in std_logic_vector(7 downto 0)
169 );
170 end component;
171
172
173 --+-----------------------------------------------------------------------------+
174 --| CONSTANTS |
175 --+-----------------------------------------------------------------------------+
176 --+-----------------------------------------------------------------------------+
177 --| SIGNALS |
178 --+-----------------------------------------------------------------------------+
179
180 signal wb_adr : std_logic_vector(24 downto 1);
181 signal wb_dat_out : std_logic_vector(15 downto 0);
182 signal wb_dat_in : std_logic_vector(15 downto 0);
183 signal wb_sel : std_logic_vector(1 downto 0);
184 signal wb_we : std_logic;
185 signal wb_stb : std_logic;
186 signal wb_cyc : std_logic;
187 signal wb_ack : std_logic;
188 signal wb_err : std_logic;
189 signal wb_int : std_logic;
190
191
192 begin
193
194 --+-----------------------------------------+
195 --| PCI Target |
196 --+-----------------------------------------+
197
198 u_pci: component pci32tlite
199 port map(
200 clk33 => PCI_CLK,
201 nrst => PCI_nRES,
202 ad => PCI_AD,
203 cbe => PCI_CBE,
204 par => PCI_PAR,
205 frame => PCI_nFRAME,
206 irdy => PCI_nIRDY,
207 trdy => PCI_nTRDY,
208 devsel => PCI_nDEVSEL,
209 stop => PCI_nSTOP,
210 idsel => PCI_IDSEL,
211 perr => PCI_nPERR,
212 serr => PCI_nSERR,
213 intb => PCI_nINT,
214 wb_adr_o => wb_adr,
215 wb_dat_i => wb_dat_out,
216 wb_dat_o => wb_dat_in,
217 wb_sel_o => wb_sel,
218 wb_we_o => wb_we,
219 wb_stb_o => wb_stb,
220 wb_cyc_o => wb_cyc,
221 wb_ack_i => wb_ack,
222 wb_err_i => wb_err,
223 wb_int_i => wb_int
224 -- debug_init => LED3,
225 -- debug_access => LED2
226 );
227
228 --+-----------------------------------------+
229 --| WB-7seg |
230 --+-----------------------------------------+
231
232 my_heartbeat: component heartbeat
233 port map(
234 clk_i => PCI_CLK,
235 nrst_i => PCI_nRES,
236 led2_o => LED2,
237 led3_o => LED3,
238 led4_o => LED4,
239 led5_o => LED5
240 );
241
242 end dhwk_arch;
Impressum, Datenschutz