move, ident
[raggedstone] / dhwk / source / COMM_FSM.vhd
1 -- J.STELZNER
2 -- INFORMATIK-3 LABOR
3 -- 23.08.2006
4 -- File: COMM_FSM.VHD
5
6 library ieee;
7 use ieee.std_logic_1164.all ;
8
9 entity COMM_FSM is
10 port
11 (
12 PCI_CLOCK :in std_logic;
13 PCI_RSTn :in std_logic;
14 IO_READ :in std_logic;
15 IO_WRITE :in std_logic;
16 CONF_READ :in std_logic;
17 CONF_WRITE :in std_logic;
18 DEVSELn :in std_logic;
19
20 IO_RD_COM : out std_logic;--> MUX_SEL(0)
21 CF_RD_COM :out std_logic;
22 IO_WR_COM :out std_logic;
23 CF_WR_COM :out std_logic
24 );
25 end entity COMM_FSM ;
26
27 architecture COMM_FSM_DESIGN of COMM_FSM is
28
29
30 --**********************************************************
31 --*** COMMAND FSM CODIERUNG ***
32 --**********************************************************
33 --
34 --
35 -- |--------- IO_RD_COM
36 -- ||-------- CF_RD_COM
37 -- |||------- IO_WR_COM
38 -- ||||------ CF_WR_COM
39 -- ||||
40 constant ST_IDLE_COMM :std_logic_vector (3 downto 0) := "0000" ;--
41 constant ST_CONF_WRITE :std_logic_vector (3 downto 0) := "0001" ;--
42 constant ST_IO_WRITE :std_logic_vector (3 downto 0) := "0010" ;--
43 constant ST_CONF_READ :std_logic_vector (3 downto 0) := "0100" ;--
44 constant ST_IO_READ :std_logic_vector (3 downto 0) := "1000" ;--
45
46 signal COMM_STATE :std_logic_vector (3 downto 0);
47
48 --************************************************************
49 --*** FSM SPEICHER-AUTOMAT ***
50 --************************************************************
51
52 attribute syn_state_machine : boolean;
53 attribute syn_state_machine of COMM_STATE : signal is false;
54
55 begin
56
57 --**********************************************************
58 --*** COMMAND FSM ***
59 --**********************************************************
60
61 process (PCI_CLOCK, PCI_RSTn)
62 begin
63 if PCI_RSTn = '0' then COMM_STATE <= "0000";
64
65 elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
66
67 case COMM_STATE is
68
69 when ST_IDLE_COMM =>
70 if IO_READ = '1' then COMM_STATE <= ST_IO_READ;
71
72 elsif CONF_READ = '1' then COMM_STATE <= ST_CONF_READ;
73
74 elsif IO_WRITE = '1' then COMM_STATE <= ST_IO_WRITE;
75
76 elsif CONF_WRITE = '1' then COMM_STATE <= ST_CONF_WRITE;
77
78 else COMM_STATE <= ST_IDLE_COMM;
79 end if;
80
81 when ST_IO_READ => if DEVSELn = '1' then COMM_STATE <= ST_IDLE_COMM; end if;
82 when ST_CONF_READ => if DEVSELn = '1' then COMM_STATE <= ST_IDLE_COMM; end if;
83 when ST_IO_WRITE => if DEVSELn = '1' then COMM_STATE <= ST_IDLE_COMM; end if;
84 when ST_CONF_WRITE => if DEVSELn = '1' then COMM_STATE <= ST_IDLE_COMM; end if;
85
86 when others => COMM_STATE <= ST_IDLE_COMM;
87
88 end case; -- COMM_STATE
89 end if; -- CLOCK
90 end process; -- PROCESS
91
92 IO_RD_COM <= COMM_STATE(3);
93 CF_RD_COM <= COMM_STATE(2);
94 IO_WR_COM <= COMM_STATE(1);
95 CF_WR_COM <= COMM_STATE(0);
96
97 end architecture COMM_FSM_DESIGN ;
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