git.zerfleddert.de Git - raggedstone/blob - ethernet/source/ethernet/eth_outputcontrol.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  eth_outputcontrol.v                                         ////
   4 ////                                                              ////
   5 ////  This file is part of the Ethernet IP core project           ////
   6 ////  http://www.opencores.org/projects/ethmac/                   ////
   7 ////                                                              ////
   8 ////  Author(s):                                                  ////
   9 ////      - Igor Mohor (igorM@opencores.org)                      ////
  10 ////                                                              ////
  11 ////  All additional information is avaliable in the Readme.txt   ////
  12 ////  file.                                                       ////
  13 ////                                                              ////
  14 //////////////////////////////////////////////////////////////////////
  15 ////                                                              ////
  16 //// Copyright (C) 2001 Authors                                   ////
  17 ////                                                              ////
  18 //// This source file may be used and distributed without         ////
  19 //// restriction provided that this copyright statement is not    ////
  20 //// removed from the file and that any derivative work contains  ////
  21 //// the original copyright notice and the associated disclaimer. ////
  22 ////                                                              ////
  23 //// This source file is free software; you can redistribute it   ////
  24 //// and/or modify it under the terms of the GNU Lesser General   ////
  25 //// Public License as published by the Free Software Foundation; ////
  26 //// either version 2.1 of the License, or (at your option) any   ////
  27 //// later version.                                               ////
  28 ////                                                              ////
  29 //// This source is distributed in the hope that it will be       ////
  30 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  31 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  32 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  33 //// details.                                                     ////
  34 ////                                                              ////
  35 //// You should have received a copy of the GNU Lesser General    ////
  36 //// Public License along with this source; if not, download it   ////
  37 //// from http://www.opencores.org/lgpl.shtml                     ////
  38 ////                                                              ////
  39 //////////////////////////////////////////////////////////////////////
  40 //
  41 // CVS Revision History
  42 //
  43 // $Log: eth_outputcontrol.v,v $
  44 // Revision 1.1  2007-03-20 17:50:56  sithglan
  45 // add shit
  46 //
  47 // Revision 1.4  2002/07/09 20:11:59  mohor
  48 // Comment removed.
  49 //
  50 // Revision 1.3  2002/01/23 10:28:16  mohor
  51 // Link in the header changed.
  52 //
  53 // Revision 1.2  2001/10/19 08:43:51  mohor
  54 // eth_timescale.v changed to timescale.v This is done because of the
  55 // simulation of the few cores in a one joined project.
  56 //
  57 // Revision 1.1  2001/08/06 14:44:29  mohor
  58 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
  59 // Include files fixed to contain no path.
  60 // File names and module names changed ta have a eth_ prologue in the name.
  61 // File eth_timescale.v is used to define timescale
  62 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
  63 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
  64 // and Mdo_OE. The bidirectional signal must be created on the top level. This
  65 // is done due to the ASIC tools.
  66 //
  67 // Revision 1.1  2001/07/30 21:23:42  mohor
  68 // Directory structure changed. Files checked and joind together.
  69 //
  70 // Revision 1.3  2001/06/01 22:28:56  mohor
  71 // This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
  72 //
  73 //
  74
  75 `include "timescale.v"
  76
  77 module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
  78
  79 parameter Tp = 1;
  80
  81 input         Clk;                // Host Clock
  82 input         Reset;              // General Reset
  83 input         WriteOp;            // Write Operation Latch (When asserted, write operation is in progress)
  84 input         NoPre;              // No Preamble (no 32-bit preamble)
  85 input         InProgress;         // Operation in progress
  86 input         ShiftedBit;         // This bit is output of the shift register and is connected to the Mdo signal
  87 input   [6:0] BitCounter;         // Bit Counter
  88 input         MdcEn_n;            // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
  89
  90 output        Mdo;                // MII Management Data Output
  91 output        MdoEn;              // MII Management Data Output Enable
  92
  93 wire          SerialEn;
  94
  95 reg           MdoEn_2d;
  96 reg           MdoEn_d;
  97 reg           MdoEn;
  98
  99 reg           Mdo_2d;
 100 reg           Mdo_d;
 101 reg           Mdo;                // MII Management Data Output
 102
 103
 104
 105 // Generation of the Serial Enable signal (enables the serialization of the data)
 106 assign SerialEn =  WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
 107                 | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
 108
 109
 110 // Generation of the MdoEn signal
 111 always @ (posedge Clk or posedge Reset)
 112 begin
 113   if(Reset)
 114     begin
 115       MdoEn_2d <= #Tp 1'b0;
 116       MdoEn_d <= #Tp 1'b0;
 117       MdoEn <= #Tp 1'b0;
 118     end
 119   else
 120     begin
 121       if(MdcEn_n)
 122         begin
 123           MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32;
 124           MdoEn_d <= #Tp MdoEn_2d;
 125           MdoEn <= #Tp MdoEn_d;
 126         end
 127     end
 128 end
 129
 130
 131 // Generation of the Mdo signal.
 132 always @ (posedge Clk or posedge Reset)
 133 begin
 134   if(Reset)
 135     begin
 136       Mdo_2d <= #Tp 1'b0;
 137       Mdo_d <= #Tp 1'b0;
 138       Mdo <= #Tp 1'b0;
 139     end
 140   else
 141     begin
 142       if(MdcEn_n)
 143         begin
 144           Mdo_2d <= #Tp ~SerialEn & BitCounter<32;
 145           Mdo_d <= #Tp ShiftedBit | Mdo_2d;
 146           Mdo <= #Tp Mdo_d;
 147         end
 148     end
 149 end
 150
 151
 152
 153 endmodule