1 //////////////////////////////////////////////////////////////////////
3 //// eth_txethmac.v ////
5 //// This file is part of the Ethernet IP core project ////
6 //// http://www.opencores.org/projects/ethmac/ ////
9 //// - Igor Mohor (igorM@opencores.org) ////
10 //// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
11 //// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
13 //// All additional information is avaliable in the Readme.txt ////
16 //////////////////////////////////////////////////////////////////////
18 //// Copyright (C) 2001 Authors ////
20 //// This source file may be used and distributed without ////
21 //// restriction provided that this copyright statement is not ////
22 //// removed from the file and that any derivative work contains ////
23 //// the original copyright notice and the associated disclaimer. ////
25 //// This source file is free software; you can redistribute it ////
26 //// and/or modify it under the terms of the GNU Lesser General ////
27 //// Public License as published by the Free Software Foundation; ////
28 //// either version 2.1 of the License, or (at your option) any ////
29 //// later version. ////
31 //// This source is distributed in the hope that it will be ////
32 //// useful, but WITHOUT ANY WARRANTY; without even the implied ////
33 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
34 //// PURPOSE. See the GNU Lesser General Public License for more ////
37 //// You should have received a copy of the GNU Lesser General ////
38 //// Public License along with this source; if not, download it ////
39 //// from http://www.opencores.org/lgpl.shtml ////
41 //////////////////////////////////////////////////////////////////////
43 // CVS Revision History
45 // $Log: eth_txethmac.v,v $
46 // Revision 1.1 2007-03-20 17:50:56 sithglan
49 // Revision 1.9 2005/02/21 11:25:28 igorm
52 // Revision 1.8 2003/01/30 13:33:24 mohor
53 // When padding was enabled and crc disabled, frame was not ended correctly.
55 // Revision 1.7 2002/02/26 16:24:01 mohor
56 // RetryCntLatched was unused and removed from design
58 // Revision 1.6 2002/02/22 12:56:35 mohor
59 // Retry is not activated when a Tx Underrun occured
61 // Revision 1.5 2002/02/11 09:18:22 mohor
62 // Tx status is written back to the BD.
64 // Revision 1.4 2002/01/23 10:28:16 mohor
65 // Link in the header changed.
67 // Revision 1.3 2001/10/19 08:43:51 mohor
68 // eth_timescale.v changed to timescale.v This is done because of the
69 // simulation of the few cores in a one joined project.
71 // Revision 1.2 2001/09/11 14:17:00 mohor
72 // Few little NCSIM warnings fixed.
74 // Revision 1.1 2001/08/06 14:44:29 mohor
75 // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
76 // Include files fixed to contain no path.
77 // File names and module names changed ta have a eth_ prologue in the name.
78 // File eth_timescale.v is used to define timescale
79 // All pin names on the top module are changed to contain _I, _O or _OE at the end.
80 // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
81 // and Mdo_OE. The bidirectional signal must be created on the top level. This
82 // is done due to the ASIC tools.
84 // Revision 1.1 2001/07/30 21:23:42 mohor
85 // Directory structure changed. Files checked and joind together.
87 // Revision 1.3 2001/06/19 18:16:40 mohor
88 // TxClk changed to MTxClk (as discribed in the documentation).
89 // Crc changed so only one file can be used instead of two.
91 // Revision 1.2 2001/06/19 10:38:08 mohor
92 // Minor changes in header.
94 // Revision 1.1 2001/06/19 10:27:58 mohor
95 // TxEthMAC initial release.
100 `include "timescale.v"
103 module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
104 Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
105 IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
106 MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
107 ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
108 LateCollision, DeferIndication, StatePreamble, StateData
115 input MTxClk; // Transmit clock (from PHY)
116 input Reset; // Reset
117 input TxStartFrm; // Transmit packet start frame
118 input TxEndFrm; // Transmit packet end frame
119 input TxUnderRun; // Transmit packet under-run
120 input [7:0] TxData; // Transmit packet data byte
121 input CarrierSense; // Carrier sense (synchronized)
122 input Collision; // Collision (synchronized)
123 input Pad; // Pad enable (from register)
124 input CrcEn; // Crc enable (from register)
125 input FullD; // Full duplex (from register)
126 input HugEn; // Huge packets enable (from register)
127 input DlyCrcEn; // Delayed Crc enabled (from register)
128 input [15:0] MinFL; // Minimum frame length (from register)
129 input [15:0] MaxFL; // Maximum frame length (from register)
130 input [6:0] IPGT; // Back to back transmit inter packet gap parameter (from register)
131 input [6:0] IPGR1; // Non back to back transmit inter packet gap parameter IPGR1 (from register)
132 input [6:0] IPGR2; // Non back to back transmit inter packet gap parameter IPGR2 (from register)
133 input [5:0] CollValid; // Valid collision window (from register)
134 input [3:0] MaxRet; // Maximum retry number (from register)
135 input NoBckof; // No backoff (from register)
136 input ExDfrEn; // Excessive defferal enable (from register)
138 output [3:0] MTxD; // Transmit nibble (to PHY)
139 output MTxEn; // Transmit enable (to PHY)
140 output MTxErr; // Transmit error (to PHY)
141 output TxDone; // Transmit packet done (to RISC)
142 output TxRetry; // Transmit packet retry (to RISC)
143 output TxAbort; // Transmit packet abort (to RISC)
144 output TxUsedData; // Transmit packet used data (to RISC)
145 output WillTransmit; // Will transmit (to RxEthMAC)
146 output ResetCollision; // Reset Collision (for synchronizing collision)
147 output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes
150 output MaxCollisionOccured;
151 output LateCollision;
152 output DeferIndication;
153 output StatePreamble;
154 output [1:0] StateData;
165 reg StopExcessiveDeferOccured;
169 reg PacketFinished_q;
173 wire ExcessiveDeferOccured;
176 wire [1:0] StartData;
195 wire [2:0] DlyCrcCnt;
205 wire RandomEqByteCnt;
206 wire PacketFinished_d;
210 assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
212 assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
214 assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn);
216 assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
218 assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
220 // assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
221 assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
223 assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
225 assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
227 assign StateSFD = StatePreamble & NibCntEq15;
229 assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
232 // StopExcessiveDeferOccured
233 always @ (posedge MTxClk or posedge Reset)
236 StopExcessiveDeferOccured <= #Tp 1'b0;
240 StopExcessiveDeferOccured <= #Tp 1'b0;
242 if(ExcessiveDeferOccured)
243 StopExcessiveDeferOccured <= #Tp 1'b1;
249 always @ (posedge MTxClk or posedge Reset)
252 ColWindow <= #Tp 1'b1;
255 if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
256 ColWindow <= #Tp 1'b0;
258 if(StateIdle | StateIPG)
259 ColWindow <= #Tp 1'b1;
265 always @ (posedge MTxClk or posedge Reset)
268 StatusLatch <= #Tp 1'b0;
272 StatusLatch <= #Tp 1'b0;
274 if(ExcessiveDeferOccured | StateIdle)
275 StatusLatch <= #Tp 1'b1;
280 // Transmit packet used data
281 always @ (posedge MTxClk or posedge Reset)
284 TxUsedData <= #Tp 1'b0;
286 TxUsedData <= #Tp |StartData;
290 // Transmit packet done
291 always @ (posedge MTxClk or posedge Reset)
297 if(TxStartFrm & ~StatusLatch)
306 // Transmit packet retry
307 always @ (posedge MTxClk or posedge Reset)
313 if(TxStartFrm & ~StatusLatch)
322 // Transmit packet abort
323 always @ (posedge MTxClk or posedge Reset)
329 if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
339 always @ (posedge MTxClk or posedge Reset)
342 RetryCnt[3:0] <= #Tp 4'h0;
345 if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
346 | StateJam & NibCntEq7 & (~ColWindow | RetryMax))
347 RetryCnt[3:0] <= #Tp 4'h0;
349 if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
350 RetryCnt[3:0] <= #Tp RetryCnt[3:0] + 1'b1;
355 assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
359 always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
363 MTxD_d[3:0] = TxData[3:0]; // Lower nibble
366 MTxD_d[3:0] = TxData[7:4]; // Higher nibble
369 MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]}; // Crc
372 MTxD_d[3:0] = 4'h9; // Jam pattern
376 MTxD_d[3:0] = 4'hd; // SFD
378 MTxD_d[3:0] = 4'h5; // Preamble
385 always @ (posedge MTxClk or posedge Reset)
390 MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
395 always @ (posedge MTxClk or posedge Reset)
398 MTxD[3:0] <= #Tp 4'h0;
400 MTxD[3:0] <= #Tp MTxD_d[3:0];
405 always @ (posedge MTxClk or posedge Reset)
410 MTxErr <= #Tp TooBig | UnderRun;
415 always @ (posedge MTxClk or posedge Reset)
418 WillTransmit <= #Tp 1'b0;
420 WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
424 assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
428 always @ (posedge MTxClk or posedge Reset)
432 PacketFinished <= #Tp 1'b0;
433 PacketFinished_q <= #Tp 1'b0;
437 PacketFinished <= #Tp PacketFinished_d;
438 PacketFinished_q <= #Tp PacketFinished;
443 // Connecting module Counters
444 eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
445 .StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
446 .StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
447 .StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
448 .Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
449 .PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
450 .StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
451 .NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
452 .DlyCrcCnt(DlyCrcCnt)
456 // Connecting module StateM
457 eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
458 .NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
459 .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
460 .UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
461 .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
462 .NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
463 .NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
464 .StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
465 .StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
466 .StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
467 .StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
475 assign Enable_Crc = ~StateFCS;
477 assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
478 assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
479 assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
480 assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
482 assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
485 // Connecting module Crc
486 eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
487 .Crc(Crc), .CrcError(CrcError)
491 // Connecting module Random
492 eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
493 .NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));