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[raggedstone] / heartbeat / source / vga_main.vhd
1 ---------------------------------------------------------------------
2 -- vga_main.vhd Demo VGA configuration module.
3 ---------------------------------------------------------------------
4 -- Author: Barron Barnett
5 -- Copyright 2004 Digilent, Inc.
6 ---------------------------------------------------------------------
7 --
8 -- This project is compatible with Xilinx ISE or Xilinx WebPack tools.
9 --
10 -- Inputs:
11 -- mclk - System Clock
12 -- Outputs:
13 -- hs - Horizontal Sync
14 -- vs - Vertical Sync
15 -- red - Red Output
16 -- grn - Green Output
17 -- blu - Blue Output
18 --
19 -- This module creates a three line pattern on a vga display using a
20 -- a vertical refresh rate of 60Hz. This is done by dividing the
21 -- system clock in half and using that for the pixel clock. This in
22 -- turn drives the vertical sync when the horizontal sync has reached
23 -- its reset point. All data displayed is done by basic value
24 -- comparisons.
25 ------------------------------------------------------------------------
26 -- Revision History:
27 -- 07/01/2004(BarronB): created
28 ------------------------------------------------------------------------
29 library IEEE;
30 use IEEE.STD_LOGIC_1164.ALL;
31 use IEEE.STD_LOGIC_ARITH.ALL;
32 use IEEE.STD_LOGIC_UNSIGNED.ALL;
33
34
35 entity vgaController is
36 Port ( mclk : in std_logic;
37 hs : out std_logic;
38 vs : out std_logic;
39 red : out std_logic;
40 grn : out std_logic;
41 blu : out std_logic);
42 end vgaController;
43
44 architecture Behavioral of vgaController is
45
46
47 constant hpixels : std_logic_vector(9 downto 0) := "1100100000"; --Value of pixels in a horizontal line
48 constant vlines : std_logic_vector(9 downto 0) := "1000001001"; --Number of horizontal lines in the display
49
50 constant hbp : std_logic_vector(9 downto 0) := "0010010000"; --Horizontal back porch
51 constant hfp : std_logic_vector(9 downto 0) := "1100010000"; --Horizontal front porch
52 constant vbp : std_logic_vector(9 downto 0) := "0000011111"; --Vertical back porch
53 constant vfp : std_logic_vector(9 downto 0) := "0111111111"; --Vertical front porch
54
55 signal hc, vc : std_logic_vector(9 downto 0); --These are the Horizontal and Vertical counters
56 signal clkdiv : std_logic; --Clock divider
57 signal vidon : std_logic; --Tells whether or not its ok to display data
58 signal vsenable : std_logic; --Enable for the Vertical counter
59
60 begin
61 --This cuts the 50Mhz clock in half
62 process(mclk)
63 begin
64 if(mclk = '1' and mclk'EVENT) then
65 clkdiv <= not clkdiv;
66 end if;
67 end process;
68
69 --Runs the horizontal counter
70 process(clkdiv)
71 begin
72 if(clkdiv = '1' and clkdiv'EVENT) then
73 if hc = hpixels then --If the counter has reached the end of pixel count
74 hc <= "0000000000"; --reset the counter
75 vsenable <= '1'; --Enable the vertical counter to increment
76 else
77 hc <= hc + 1; --Increment the horizontal counter
78 vsenable <= '0'; --Leave the vsenable off
79 end if;
80 end if;
81 end process;
82
83 hs <= '1' when hc(9 downto 7) = "000" else '0'; --Horizontal Sync Pulse
84
85 process(clkdiv)
86 begin
87 if(clkdiv = '1' and clkdiv'EVENT and vsenable = '1') then --Increment when enabled
88 if vc = vlines then --Reset when the number of lines is reached
89 vc <= "0000000000";
90 else vc <= vc + 1; --Increment the vertical counter
91 end if;
92 end if;
93 end process;
94
95 vs <= '1' when vc(9 downto 1) = "000000000" else '0'; --Vertical Sync Pulse
96
97 red <= '1' when (hc = "1010101100" and vidon ='1') else '0'; --Red pixel on at a specific horizontal count
98 grn <= '1' when (hc = "0100000100" and vidon ='1') else '0'; --Green pixel on at a specific horizontal count
99 blu <= '1' when (vc = "0100100001" and vidon ='1') else '0'; --Blue pixel on at a specific vertical count
100
101 vidon <= '1' when (((hc < hfp) and (hc > hbp)) or ((vc < vfp) and (vc > vbp))) else '0'; --Enable video out when within the porches
102
103 end Behavioral;
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