c7982941f1283337f185315ab2d796ae4ec64273
[raggedstone] / heartbeat / source / top_raggedstone.vhd
1 --+-------------------------------------------------------------------------------------------------+
2 --| |
3 --| File: top.vhd |
4 --| |
5 --| Components: pci32lite.vhd |
6 --| pciwbsequ.vhd |
7 --| pcidmux.vhd |
8 --| pciregs.vhd |
9 --| pcipargen.vhd |
10 --| -- Libs -- |
11 --| ona.vhd |
12 --| |
13 --| Description: RS1 PCI Demo : (TOP) Main file. |
14 --| |
15 --| |
16 --| |
17 --+-------------------------------------------------------------------------------------------------+
18 --| |
19 --| Revision history : |
20 --| Date Version Author Description |
21 --| |
22 --| |
23 --| To do: |
24 --| |
25 --+-------------------------------------------------------------------------------------------------+
26
27
28 --+-----------------------------------------------------------------------------+
29 --| LIBRARIES |
30 --+-----------------------------------------------------------------------------+
31
32 library ieee;
33 use ieee.std_logic_1164.all;
34 use ieee.std_logic_arith.all;
35 use ieee.std_logic_unsigned.all;
36
37 --+-----------------------------------------------------------------------------+
38 --| ENTITY |
39 --+-----------------------------------------------------------------------------+
40
41 entity raggedstone is
42 port (
43
44 -- General
45 PCI_CLK : in std_logic;
46 PCI_nRES : in std_logic;
47
48 -- PCI target 32bits
49 PCI_AD : inout std_logic_vector(31 downto 0);
50 PCI_CBE : in std_logic_vector(3 downto 0);
51 PCI_PAR : out std_logic;
52 PCI_nFRAME : in std_logic;
53 PCI_nIRDY : in std_logic;
54 PCI_nTRDY : out std_logic;
55 PCI_nDEVSEL : out std_logic;
56 PCI_nSTOP : out std_logic;
57 PCI_IDSEL : in std_logic;
58 PCI_nPERR : out std_logic;
59 PCI_nSERR : out std_logic;
60 PCI_nINT : out std_logic;
61
62 -- debug signals
63 LED3 : out std_logic;
64 LED2 : out std_logic;
65 LED4 : out std_logic;
66 LED5 : out std_logic;
67 IDE1 : out std_logic;
68 IDE2 : out std_logic;
69 IDE3 : out std_logic;
70 IDE4 : out std_logic
71
72 );
73 end raggedstone;
74
75
76 --+-----------------------------------------------------------------------------+
77 --| ARCHITECTURE |
78 --+-----------------------------------------------------------------------------+
79
80 architecture raggedstone_arch of raggedstone is
81
82
83 --+-----------------------------------------------------------------------------+
84 --| COMPONENTS |
85 --+-----------------------------------------------------------------------------+
86
87 component pci32tlite
88 port (
89
90 -- General
91 clk33 : in std_logic;
92 nrst : in std_logic;
93
94 -- PCI target 32bits
95 ad : inout std_logic_vector(31 downto 0);
96 cbe : in std_logic_vector(3 downto 0);
97 par : out std_logic;
98 frame : in std_logic;
99 irdy : in std_logic;
100 trdy : out std_logic;
101 devsel : out std_logic;
102 stop : out std_logic;
103 idsel : in std_logic;
104 perr : out std_logic;
105 serr : out std_logic;
106 intb : out std_logic;
107
108 -- Master whisbone
109 wb_adr_o : out std_logic_vector(24 downto 1);
110 wb_dat_i : in std_logic_vector(15 downto 0);
111 wb_dat_o : out std_logic_vector(15 downto 0);
112 wb_sel_o : out std_logic_vector(1 downto 0);
113 wb_we_o : out std_logic;
114 wb_stb_o : out std_logic;
115 wb_cyc_o : out std_logic;
116 wb_ack_i : in std_logic;
117 wb_err_i : in std_logic;
118 wb_int_i : in std_logic;
119
120 -- debug signals
121 debug_init : out std_logic;
122 debug_access : out std_logic
123
124 );
125 end component;
126
127 component heartbeat
128 port (
129 clk_i : in std_logic;
130 nrst_i : in std_logic;
131 led2_o : out std_logic;
132 led3_o : out std_logic;
133 led4_o : out std_logic;
134 led5_o : out std_logic;
135 led6_o : out std_logic;
136 led7_o : out std_logic;
137 led8_o : out std_logic;
138 led9_o : out std_logic
139 );
140 end component;
141
142
143 --+-----------------------------------------------------------------------------+
144 --| CONSTANTS |
145 --+-----------------------------------------------------------------------------+
146 --+-----------------------------------------------------------------------------+
147 --| SIGNALS |
148 --+-----------------------------------------------------------------------------+
149
150 signal wb_adr : std_logic_vector(24 downto 1);
151 signal wb_dat_out : std_logic_vector(15 downto 0);
152 signal wb_dat_in : std_logic_vector(15 downto 0);
153 signal wb_sel : std_logic_vector(1 downto 0);
154 signal wb_we : std_logic;
155 signal wb_stb : std_logic;
156 signal wb_cyc : std_logic;
157 signal wb_ack : std_logic;
158 signal wb_err : std_logic;
159 signal wb_int : std_logic;
160
161
162 begin
163
164 --+-----------------------------------------+
165 --| PCI Target |
166 --+-----------------------------------------+
167
168 u_pci: component pci32tlite
169 port map(
170 clk33 => PCI_CLK,
171 nrst => PCI_nRES,
172 ad => PCI_AD,
173 cbe => PCI_CBE,
174 par => PCI_PAR,
175 frame => PCI_nFRAME,
176 irdy => PCI_nIRDY,
177 trdy => PCI_nTRDY,
178 devsel => PCI_nDEVSEL,
179 stop => PCI_nSTOP,
180 idsel => PCI_IDSEL,
181 perr => PCI_nPERR,
182 serr => PCI_nSERR,
183 intb => PCI_nINT,
184 wb_adr_o => wb_adr,
185 wb_dat_i => wb_dat_out,
186 wb_dat_o => wb_dat_in,
187 wb_sel_o => wb_sel,
188 wb_we_o => wb_we,
189 wb_stb_o => wb_stb,
190 wb_cyc_o => wb_cyc,
191 wb_ack_i => wb_ack,
192 wb_err_i => wb_err,
193 wb_int_i => wb_int
194 -- debug_init => LED3,
195 -- debug_access => LED2
196 );
197
198 --+-----------------------------------------+
199 --| WB-7seg |
200 --+-----------------------------------------+
201
202 my_heartbeat: component heartbeat
203 port map(
204 clk_i => PCI_CLK,
205 nrst_i => PCI_nRES,
206 led2_o => LED2,
207 led3_o => LED3,
208 led4_o => LED4,
209 led5_o => LED5,
210 led6_o => IDE1,
211 led7_o => IDE2,
212 led8_o => IDE3,
213 led9_o => IDE4
214 );
215
216 end raggedstone_arch;
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