c8ecfa7859a450832b4e4dda1e251e632e300713
[raggedstone] / dhwk / source / pci / parity_out.vhd
1 -- J.STELZNER
2 -- INFORMATIK-3 LABOR
3 -- 23.08.2006
4 -- File: PARITY_OUT.VHD
5
6 library ieee;
7 use ieee.std_logic_1164.all;
8
9 entity PARITY_OUT is
10 port(
11 PCI_CLOCK :in std_logic;
12 PCI_RSTn :in std_logic;
13 PAR_IN :in std_logic_vector ( 2 downto 0);
14 PAR_REG :in std_logic;
15 SERR_CHECK :in std_logic;
16 PERR_CHECK :in std_logic;
17 OE_PCI_PAR :in std_logic;
18 OE_PCI_PERR :in std_logic;
19 PA_ER_RE :in std_logic;
20 SERR_ENA :in std_logic;
21 PCI_PAR_IN :in std_logic;
22 PERR :out std_logic;
23 SERR :out std_logic;
24 PCI_PERRn :out std_logic; -- s/t/s
25 PCI_SERRn :out std_logic; -- o/d
26 PCI_PAR :out std_logic -- t/s
27 );
28 end entity PARITY_OUT;
29
30 architecture PARITY_OUT_DESIGN of PARITY_OUT is
31
32 signal PAR :std_logic;
33 signal PAR_FF :std_logic;
34 signal SERR_FF :std_logic;
35 signal PERR_FF :std_logic;
36
37 begin
38
39 PAR <= ( PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) );
40
41 process (PCI_CLOCK, PCI_RSTn)
42 begin
43 if PCI_RSTn = '0' then PAR_FF <= '0';
44 PERR_FF <= '0';
45 SERR_FF <= '0';
46
47 elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then
48 SERR_FF <= ((PCI_PAR_IN xor PAR) and SERR_CHECK) and PA_ER_RE and SERR_ENA and (not SERR_FF);
49 PERR_FF <= ((PCI_PAR_IN xor PAR) and PERR_CHECK) and (not PERR_FF);
50 end if;
51 end process;
52
53 SERR <= SERR_FF;
54 PERR <= PERR_FF;
55
56 PCI_PAR <= PAR_FF when OE_PCI_PAR = '1' else 'Z';
57 PCI_SERRn <= '0' when SERR_FF = '1' else 'Z';
58 PCI_PERRn <= not PERR_FF when OE_PCI_PERR = '1' and PA_ER_RE = '1' else 'Z';
59
60 end architecture PARITY_OUT_DESIGN;
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